Kernel mechanisms with dynamic task-aware scheduling to reduce resource contention in NUMA multi-core systems

Chiang, Mei‐Ling; Yang, Chieh-Jui; Tu, Shu-Wei

doi:10.1016/j.jss.2016.08.038

Cited by 9 publications

(6 citation statements)

References 3 publications

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“…The kMLB mechanism with the proposed policies can be incorporated with other mechanisms to gain further performance improvement. For example, incorporating kMLB with scheduling mechanisms that schedule complementary tasks on cores sharing resources can improve performance by reducing resource contention on multicore systems and remote memory access at the same time.…”

Section: Discussionmentioning

confidence: 99%

“…Some detect the memory access pattern for thread and data mapping on the hardware level, whereas some studies gather information from page faults or using a memory tracer tool. Several studies proposed scheduling techniques, which arrange processes to run on cores in a specific way to avoid resource contention or use the load balancing view to reduce their demand for the same resources. Some of them are designed with memory migration heuristics or strategies to reduce remote memory access.…”

Section: Technology Background and Related Workmentioning

confidence: 99%

“…In dynamic task‐aware scheduling, cores sharing resources are arranged to run complementary tasks to avoid resource contention in NUMA systems. Dynamic task‐aware scheduling monitors tasks' resource usage and classifies them as CPU‐bound or memory‐bound during runtime.…”

Section: Technology Background and Related Workmentioning

confidence: 99%

“…To reduce remote memory access and/or resource contention, existing studies use various strategies. Most of them focus on either the scheduling techniques and thread mapping strategies or memory placement and data mapping policies.…”

Section: Introductionmentioning

confidence: 99%

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Memory‐aware kernel mechanism and policies for improving internode load balancing on NUMA systems

Chiang

et al. 2019

Softw Pract Exp

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Although nonuniform memory access architecture provides better scalability for multicore systems, cores accessing memory on remote nodes take longer than those accessing on local nodes. Remote memory access accompanied by contention for internode interconnection degrades performance. Properly mapping threads to cores and data accessed to their nodes can substantially improve performance and energy efficiency. However, an operating system kernel's load-balancing activity may migrate threads across nodes, which thus messes up the thread mapping. Besides, subsequent data mapping behavior pays for the cost of page migration to reduce remote memory access. Once unsuitable threads are migrated, it is detrimental to system performance. This paper focuses on improving the kernel's internode load balancing on nonuniform memory access systems. We develop a memory-aware kernel mechanism and policies to reduce remote memory access incurred by internode thread migration. The Linux kernel's load balancing mechanism is modified to incorporate selection policies in the internode thread migration, and the kernel is modified to track the amount of memory used by each thread on each node. With this information, well-designed policies can then choose suitable threads for internode migration. The purpose is to avoid migrating a thread that might incur relatively more remote memory access and page migration. The experimental results show that with our mechanism and the proposed selection policies, the system performance is substantially increased when compared with the unmodified Linux kernel that does not consider memory usage and always migrates the first-fit thread in the runqueue that can be migrated to the target central processing unit.

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Section: Discussionmentioning

confidence: 99%

Section: Technology Background and Related Workmentioning

confidence: 99%

Section: Technology Background and Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Memory‐aware kernel mechanism and policies for improving internode load balancing on NUMA systems

Chiang

et al. 2019

Softw Pract Exp

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“…Carrefour uses hardware counters to measure performance, and, according to the authors, it takes global decisions to migrate memory pages. Several works by Chiang et al 15‐17 use several kernel modifications to improve thread allocation, deal with memory congestion, and improve locality. They have obtained important improvements in performance with PARSEC 3.0 benchmarks.…”

Section: Related Workmentioning

confidence: 99%

LBMA and IMAR²: Weighted lottery based migration strategies for NUMA multiprocessing servers

Laso

Lorenzo

Rivera

et al. 2020

Concurrency and Computation

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Summary Multicore NUMA systems present on‐board memory hierarchies and communication networks that influence performance when executing shared memory parallel codes. Characterizing this influence is complex, and understanding the effect of particular hardware configurations on different codes is of paramount importance. In this article, monitoring information extracted from hardware counters at runtime is used to characterize the behavior of each thread for an arbitrary number of multithreaded processes running in a multiprocessing environment. This characterization is given in terms of number of operations per second, operational intensity, and latency of memory accesses. We propose a runtime tool, executed in user space, that uses this information to guide two different thread migration strategies for improving execution efficiency by increasing locality and affinity without requiring any modification in the running codes. Different configurations of NAS Parallel OpenMP benchmarks running concurrently on multicore NUMA systems were used to validate the benefits of our proposal, in which up to four processes are running simultaneously. In more than the 95% of the executions of our tool, results outperform those of the operating system (OS) and produces up to 38% improvement in execution time over the OS for heterogeneous workloads, under different and realistic locality and affinity scenarios.

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CIMAR, NIMAR, and LMMA: Novel algorithms for thread and memory migrations in user space on NUMA systems using hardware counters

Laso

Lorenzo

Dominguez

et al. 2022

Future Generation Computer Systems

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Kernel mechanisms with dynamic task-aware scheduling to reduce resource contention in NUMA multi-core systems

Cited by 9 publications

References 3 publications

Memory‐aware kernel mechanism and policies for improving internode load balancing on NUMA systems

Memory‐aware kernel mechanism and policies for improving internode load balancing on NUMA systems

LBMA and IMAR²: Weighted lottery based migration strategies for NUMA multiprocessing servers

CIMAR, NIMAR, and LMMA: Novel algorithms for thread and memory migrations in user space on NUMA systems using hardware counters

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Kernel mechanisms with dynamic task-aware scheduling to reduce resource contention in NUMA multi-core systems

Cited by 9 publications

References 3 publications

Memory‐aware kernel mechanism and policies for improving internode load balancing on NUMA systems

Memory‐aware kernel mechanism and policies for improving internode load balancing on NUMA systems

LBMA and IMAR2: Weighted lottery based migration strategies for NUMA multiprocessing servers

CIMAR, NIMAR, and LMMA: Novel algorithms for thread and memory migrations in user space on NUMA systems using hardware counters

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LBMA and IMAR²: Weighted lottery based migration strategies for NUMA multiprocessing servers