Junctionless Transistor with Pulsed Shaped Dielectric (PSD-JNL): An Absorbing Structure for Nanoscale Aims

Abstract

Junctionless devices have been recently taken into consideration for the nanoscale applications. Regarding to the reliability weakness of the conventional Silicon-on-Insulator Junctionless (SOI-JLT) in nanoscale regime, this work has proposed a novel junctionless to overcome the basic problems occurring for it. The configuration of the buried oxide in the conventional JLT has been effectively modified with converting net SiO2 dielectric to a pulsed shaped dielectric including the silicon material and SiO2 material. The new configuration leaving a pulsed shaped dielectric as the buried oxide leads to the formation of an additional depletion layer in the channel region interface with the substrate. A meaningful result is that the effective channel width in the standby mode is reduced thus decreasing the leakage current, considerably. The comparisons in the cases of both DC and AC operations revealed that the proposed structure exhibits superior electrical performance in terms of the short-channel effects, thermal features, parasitic capacitance, transcondutance, output conductance, power gains, cutoff frequency, and minimum noise figure.

Electrostatically doped drain engineered DG‐TFET: Proposal and analysis

“…One possible solution emerging is the use of electrostatic doping (ED) concept, 18 wherein, gate electrode with proper work functions are used for realizing the required doping. Recently, this class of promising ED devices are studied extensively and are either called the junction-less (JL) [19][20][21][22][23][24][25] TFET or the charge-plasma (CP) [26][27][28][29] based Tunnel-FETs, to overcome the limitation of traditional chemical doping process.…”