Junctionless SOI FinFET with advanced spacer techniques for sub-3 nm technology nodes

Impact of Scaling on Nanosheet FET and CMOS Circuit Applications

“…It can be seen that the drain side potential is higher than the source due to the applied drain voltage, which causes the existence of hot electrons. 6 Moreover, for L G of 5 nm, the potential in the channel region is slightly more at the drain side compared to L G of 20 nm, which shows the drain influence over the channel region for shorter gate lengths. Furthermore, the contour plots for electric field (E) distribution are shown in Fig.…”

“…As the gate length scales down, the I ON increases as the distance between the source and drain decreases. 6 Moreover, almost a linear increment is observed with scaling and an increment of 2.1× in I ON is observed when L G is scaled from 20 nm to 5 nm. a)Further, the I OFF also get increment with downscaling of the transistor from 20 nm to 5 nm, due to the influence of SCEs.…”

“…In addition to the benefits, the uninvited disadvantageous short channel effects (SCEs) like subthreshold swing degradation, drain induced barrier lowering, threshold voltage roll-off etc., raised with downscaling of the transistor, which degrades the devices' performance severely. 5,6 To combat the SCEs, various solutions are proposed in the literature. The classical solution for this was to reduce the gate oxide thickness (t ox ) so that the electrostatic integrity of the gate over the channel is improved.…”

Spacer Engineering on Nanosheet FETs towards Device and Circuit Perspective

“…The D5 offers higher I ON compared to the D2, D3, and D4 owing to the higher fringing fields originating from the dual-k spacer. 32 The off current (I OFF ) of the device is calculated at V DS = 0.7 V and V GS = 0 V. For low power applications lowest I OFF values are essential to meet the power requirements. For different device configurations, the I OFF is shown in Fig.…”

Design and Performance Optimization of Junctionless Bottom Spacer FinFET for Digital/Analog/RF Applications at Sub-5nm Technology Node

“…11 To get rid of these adverse effects, several structures such as Double-gate (DG) FET [12][13][14] and Multigate (MG) FET 15 have been proposed by researchers. However, DG FETs exhibit a major issue with misaligned top and bottom gates, which results in a higher gate-tosource/drain overlap capacitance and higher source/drain series resistance, 16,17 Later, FinFET (a type of MGFET), 18,19 has been demonstrated to the research community to address the above issues. Microchips employing FinFETs were commercialized in the year 2010 and quickly took over the process nodes of 22 nm, 14 nm, and 7 nm.…”