Jaguar: A next-generation low-power x86-64 core

Teja, Singh; Bell, J. S.; Southard, S.

doi:10.1109/isscc.2013.6487633

Cited by 11 publications

(5 citation statements)

References 1 publication

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“…Clock gating is a standard technique to reduce clock power. It is often applied in multiple levels, particularly in big industrial designs [1][2][3][4]. This is illustrated in Fig.…”

Section: Multi-level Clock Gatingmentioning

confidence: 99%

Design and optimization of multiple-mesh clock network

Jung

Lee

Shin

2015

2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

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A clock mesh, in which clock signals are shorted at mesh grid, is less susceptible to on-chip process variation, and so it has widely been studied recently for a clock network of smaller skew. A practical design may require more than one mesh primarily because of hierarchical clock gating architecture; a single mesh, however, can also support the same architecture after some hierarchies are removed but at the cost of gating efficiency. We experimentally compare multiple-and single-mesh using a few test circuits, and show that the former consumes smaller clock power (16.3%) but exhibits larger clock skew (10.2ps) and longer clock wirelength (21.7%). We continue to study how multiple meshes should be floorplanned on the layout, specifically whether or not we allow the overlaps among meshes. The choice is translated into different physical design strategy, and causes different amount of clock skew, critical path delay, clock wirelength, and clock power consumption, which we experimentally evaluate. We give at last the comparison of clock skew variation for each mesh implementation and clock tree, and show that floorplanning of multiple meshes helps to reduce the variation of clock skew.

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“…Clock gating is a standard technique to reduce clock power. It is often applied in multiple levels, particularly in big industrial designs [1][2][3][4]. This is illustrated in Fig.…”

Section: Multi-level Clock Gatingmentioning

confidence: 99%

Design and optimization of multiple-mesh clock network

Jung

Lee

Shin

2015

2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

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show abstract

“…Clock gating is a standard technique to reduce clock power. It is often applied in multiple levels, particularly in big industrial designs [1][2][3][4]. This is illustrated Module-level clock gating Register-level clock gating Module 1 Module 2 Module 3 System-level clock gating in Fig.…”

Section: Multi-level Clock Gatingmentioning

confidence: 99%

“…Big industrial designs such as SoCs and processors are often embedded with multiple levels of clock gating to efficiently reduce the power consumption of clock distribution network [1][2][3]. Some clock gating is inserted by automatic CAD tools, e.g.…”

Section: Introductionmentioning

confidence: 99%

Design and Optimization of Multiple-Mesh Clock Network

Jung

Lee

Shin

2015

VLSI-SoC: Internet of Things Foundations

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International audienceA clock mesh, in which clock signals are shorted at mesh grid, is less susceptible to on-chip process variation, and so it has widely been studied recently for a clock network of smaller skew. A practical design may require more than one mesh primarily because of hierarchical clock gating architecture; a single mesh, however, can also support the same architecture after some hierarchies are removed but at the cost of gating efficiency. We experimentally compare multiple- and single-mesh using a few test circuits, and show that the former consumes smaller clock power (16.3 %) but exhibits larger clock skew (10.2 ps) and longer clock wirelength (21.7 %). We continue to study how multiple meshes should be floorplanned on the layout, specifically whether or not we allow the overlaps among meshes. The choice is translated into different physical design strategy, and causes different amount of clock skew, critical path delay, clock wirelength, and clock power consumption, which we experimentally evaluate. We give at last the comparison of clock skew variation for each mesh implementation and clock tree, and show that floorplanning of multiple meshes helps to reduce the variation of clock skew

show abstract

“…With CMOS technology scaling, leakage currents have become important sources of power consumption in nanoscale integrated circuits [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16]. Power/ground gating with a multi-threshold CMOS (MTCMOS) technology is the most widely used leakage power suppression technique in idle integrated circuits [1][2][3][4][5][6][7][8][9][10][11][12]15,16].…”

Section: Introductionmentioning

confidence: 99%

“…Power/ground gating with a multi-threshold CMOS (MTCMOS) technology is the most widely used leakage power suppression technique in idle integrated circuits [1][2][3][4][5][6][7][8][9][10][11][12]15,16]. In an MTCMOS circuit, high threshold voltage (high-|V th |) sleep transistors (header and/or footer) are used to cut off the power supply and/or the ground connections to an idle low threshold voltage (low-|V th |) circuit block.…”

Section: Introductionmentioning

confidence: 99%