Issues in the development of a practical NoC: the Proteo concept

Sigüenza-Tortosa, David A.; Ahonen, Toni; Nurmi, Jari

doi:10.1016/j.vlsi.2004.07.015

Cited by 33 publications

(17 citation statements)

References 12 publications

(10 reference statements)

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“…1 We assume that a deterministic routing function is utilized for routing packets, as most existing NoC architectures support only a deterministic routing function [9], [12], [13]. This is because the area-power overhead involved in adaptive routing is quite high.…”

Section: Problem Formulationmentioning

confidence: 99%

Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors

Murali¹,

Atienza

Meloni

et al. 2007

IEEE Trans. VLSI Syst.

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Abstract-Today, chip multiprocessors (CMPs) that accommodate multiple processor cores on the same chip have become a reality. As the communication complexity of such multicore systems is rapidly increasing, designing an interconnect architecture with predictable behavior is essential for proper system operation. In CMPs, general-purpose processor cores are used to run software tasks of different applications and the communication between the cores cannot be precharacterized. Designing an efficient network-on-chip (NoC)-based interconnect with predictable performance is thus a challenging task. In this paper, we address the important design issue of synthesizing the most power efficient NoC interconnect for CMPs, providing guaranteed optimum throughput and predictable performance for any application to be executed on the CMP. In our synthesis approach, we use accurate delay and power models for the network components (switches and links) that are obtained from layouts of the components using industry standard tools. The synthesis approach utilizes the floorplan knowledge of the NoC to detect timing violations on the NoC links early in the design cycle. This leads to a faster design cycle and quicker design convergence across the high-level synthesis approach and the physical implementation of the design. We validate the design flow predictability of our proposed approach by performing a layout of the NoC synthesized for a 25-core CMP. Our approach maintains the regular and predictable structure of the NoC and is applicable in practice to existing NoC architectures.

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Section: Problem Formulationmentioning

confidence: 99%

Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors

Murali¹,

Atienza

Meloni

et al. 2007

IEEE Trans. VLSI Syst.

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“…It uses very large packets (544 bytes) and buffers and, hence, requires large area. Proteo NoC also promises multiple topologies, however, currently it has been implemented only with ring topology [27]. The Proteo implementation reported in [20] also suffers from large buffering overhead due to store-and-forward routing.…”

Section: Related Workmentioning

confidence: 99%

“…Therefore, the latency is not affected notably. However, for the configurations resulting in higher latencies (configurations [12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27], the high priority offers great benefit. Regarding all configurations, high relative priority obtains 31% lower average latency and 41% lower maximum latency than the low priority.…”

Section: The Effect Of Network Parametersmentioning

confidence: 99%

HIBI Communication Network for System-on-Chip

Salminen

Kangas

Hämäläinen

et al. 2006

J VLSI Sign Process Syst Sign Image Video Technol

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This paper presents a communication network targeted for complex system-on-chip (SoC) and network-on-chip (NoC) designs. The Heterogeneous IP Block Interconnection (HIBI) aims at maximum efficiency and minimum energy per transmitted bit combined with quality-of-service (QoS) in transfers. Other features include support for hierarchical topologies with several clock domains, flexible scalability, and runtime reconfiguration of network parameters. HIBI is intended for integrating coarse-grain components such as intellectual property (IP) blocks that have size of thousands of gates. HIBI has been implemented in VHDL and SystemC and synthesized on several CMOS technologies and on FPGA. A 32-bit wrapper requires 5400 gates and runs with 315 MHz on 0.18 μm technology which shows that only minimal area overhead is paid for the advanced features. The area and frequency results are well comparable to other NoC proposals. Furthermore, data transfers are shown to approach the maximum theoretical performance for protocol efficiency. HIBI network is accompanied with a design framework with tools for optimizing the system through automated design space exploration.

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“…In [8] a fully synchronous, pipelined NoC called ×pipes has been described, featuring wormhole switching with static routing tables and software tools for automatic instantiation of application specific NoCs. A similar NoC, called Proteo and developed in Tampere University of Technology, is introducing the Globally-Asynchronous Locally-Synchronous (GALS) approach [9] in order to solve the problem of the clock skew and delay. Finally, a NoC with Spatial Division Multiple Access has been introduced in [10], in contrast to the much more widely used TDMA technique.…”

Section: Introduction and Related Workmentioning

confidence: 99%

Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications

Milojevic

Montperrus²,

Verkest

2008

J Sign Process Syst Sign Image Video Technol

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In the near future, small electronic hand-held devices will be equipped with digital cameras capable of acquiring high resolution images (HDTV) at realtime rates, resulting in video streams of dozens of megabytes per second. The real-time video decoding and especially encoding of such streams with AVC/ H.264 or SVC standards require a huge amount of computing power that, in the case of a hand-held device, has to be delivered under the constraint of low power dissipation. In this paper we present a MultiProcessor System-on-Chip dedicated for high performance, low-power video coding applications using Network-on-Chip (NoC) as communication infrastructure. Extensive experiments have established the power dissipation models of individual NoC components, i.e. network interfaces, routers and wires. Based on these This research has been carried out in the context of IMEC's multimode multimedia program which is partially sponsored by Samsung and Freescale. The authors would also like to thank models and the NoC topology, we build the power model of the complete NoC. For three different implementation scenarios of the AVC/H.264 simple profile encoder we derive the power dissipation of the NoC for image resolutions up to HDTV at rate of 30 frames per second. The results obtained show that for the same application mapping scenario (worst case), moving from CIF to HDTV resolution will result in a 35% increase of the total power dissipation. Finally, for HDTV resolution, the difference in power dissipation between the worst (21 mW) and the best case application mapping scenario is 26%.

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Issues in the development of a practical NoC: the Proteo concept

Cited by 33 publications

References 12 publications

Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors

Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors

HIBI Communication Network for System-on-Chip

Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications

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