ISP: An Optimal Out-of-Core Image-Set Processing Streaming Architecture for Parallel Heterogeneous Systems

Ha, Linh K.; Krüger, Jens; Comba, João Luiz Dihl; Silva, C. T.; Joshi, Sarang

doi:10.1109/tvcg.2012.32

Cited by 6 publications

(3 citation statements)

References 42 publications

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“…The work in [Ha et al, 2012] proposed an Image-Set Processing streaming framework that uses the power of a heterogeneous CPU/GPU platform. In that work, the CPU is responsible for reading and writing an image while all image processing steps are done by the GPU.…”

Section: Streaming Image Processing With Hardware Accelerationmentioning

confidence: 99%

Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

Pham‐Quoc¹,

Heisswolf²,

Werner³

et al. 2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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Heterogeneous multicore systems are becoming increasingly important as the need for computation power grows, especially when we are entering into the big data era. As one of the main trends in heterogeneous multicore, hardware accelerator systems provide application specific hardware circuits and are thus more energy efficient and have higher performance than general purpose processors, while still providing a large degree of flexibility. However, system performance dose not scale when increasing the number of processing cores due to the communication overhead which increases greatly with the increasing number of cores. Although data communication is a primary anticipated bottleneck for system performance, the interconnect design for data communication among the accelerator kernels has not been well addressed in hardware accelerator systems. A simple bus or shared memory is usually used for data communication between the accelerator kernels. In this dissertation, we address the issue of interconnect design for heterogeneous hardware accelerator systems.Evidently, there are dependencies among computations, since data produced by one kernel may be needed by another kernel. Data communication patterns can be specific for each application and could lead to different types of interconnect. In this dissertation, we use detailed data communication profiling to design an optimized hybrid interconnect that provides the most appropriate support for the communication pattern inside an application while keeping the hardware resource usage for the interconnect minimal. Firstly, we propose a heuristicbased approach that takes application data communication profiling into account to design a hardware accelerator system with a custom interconnect. A number of solutions are considered including crossbar-based shared local memory, direct memory access (DMA) supporting parallel processing, local buffers, and hardware duplication. This approach is mainly useful for embedded system where the hardware resources are limited. Secondly, we propose an automated hybrid interconnect design using data communication profiling to define an optimized interconnect for accelerator kernels of a generic hardware accelerator system. The hybrid interconnect consists of a network-on-chip (NoC), vii viii ABSTRACT shared local memory, or both. To minimize hardware resource usage for the hybrid interconnect, we also propose an adaptive mapping algorithm to connect the computing kernels and their local memories to the proposed hybrid interconnect. Thirdly, we propose a hardware accelerator architecture to support streaming image processing. In all presented approaches, we implement the approach using a number of benchmarks on relevant reconfigurable platforms to show their effectiveness. The experimental results show that our approaches not only improve system performance but also reduce overall energy consumption compared to the baseline systems.

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Section: Streaming Image Processing With Hardware Accelerationmentioning

confidence: 99%

Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

Pham‐Quoc¹,

Heisswolf²,

Werner³

et al. 2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

View full text Add to dashboard Cite

show abstract

“…The work in [17] proposed an Image-Set Processing streaming framework that uses the power of a heterogeneous CPU/GPU platform. In that work, the CPU is responsible for reading and writing an image while all image processing steps are done by the GPU.…”

Section: B Streaming Image Processing With Hardware Accelerationmentioning

confidence: 99%

Heterogeneous hardware accelerator architecture for streaming image processing

Pham‐Quoc

Al-Ars

Bertels

2013

2013 International Conference on Advanced Technologies for Communications (ATC 2013)

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This paper proposes a heterogeneous hardware accelerator architecture to support streaming image processing. Each image in a data-set is pre-processed on a host processor and sent to hardware kernels. The host processor and the hardware kernels process a stream of images in parallel. The Convey hybrid computing system is used to develop our proposed architecture. We use the Canny edge detection algorithm as our case study. The data-set used for our experiment contains 7200 images. Experimental results show that the system with the proposed architecture achieved a speed-up of the kernels by 2.13× and of the whole application by 2.40× with respect to a software implementation running on the host processor. Moreover, our proposed system achieves 55% energy reduction compared to a hardware accelerator system without streaming support.

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“…Bu çalışma kapsamında yapılan incelemelerin daha iyi anlaşılabilmesi için kısa bir literatür taraması yapıldığında son yıllarda çalışma konusunun popüler bir konu olduğu görülmektedir [1][2][3][4][5][6][7][8][9]. Griffith ve Genant çalışmalarında kemik yoğunluğunun kemik mukavemetine olan etkisinin önemli olduğunu belirtmekle birlikte bunun tek başına yeterli olmadığını özellikle kemik mikro mimarisine ait özelliklerinde kemik mukavemetinde mutlaka dikkate alınması gereken parametreler olduğunu ortaya koymuşlardır [10].…”

Section: Introductionunclassified

Mikro Yapıların Tersine Mühendislik Yöntemleri ile Sonlu Elemanlar Yöntemi Kullanılarak Modellenmesi ve Model Geometrilerinin İncelenmesi - Effect of Micro-CT Resolutions of Voxel Based Model and Analysis Results

Güner¹,

Altıntaş²,

Ergüt³

2015

CBU J of Sci

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Çalışma konusu bilimin pek çok alanında kullanılan yöntemlerin bir arada kullanılmasını gerektiren güncel bir konudur. Tıp, malzeme ve uçak-uzay teknolojilerinin kullanıldığı pek çok alanda bu konu kapsamında kullanılan metotlar kullanılmaktadır. Öncelikle iki boyutlu tomografi taraması yapılan malzemelerin, elde edilen görüntüleri piksel piksel işlenerek üç boyutlu solid model haline getirilmesi işlemi yapılmıştır. Bu işlem aşamasının ilk kısmı ağırlıklı olarak treshold segmentasyonunun ve algoritmasının kullanılmasıyla yapılmıştır. Her iki algoritmanın seçimlik parametreleri ve sonlu eleman modellerinin geometrik morfolojisi ayrıntılı olarak incelenmiştir. Sonlu elemanlar modellerinin çözümleri ABAQUS® paket programı yardımıyla yapılmıştır. Farklı çözünürlük seçimi ile elde edilen modellerin analizleri sonucunda doğal frekansın, burkulma yükünün ve statik analiz değerlerinin değiştiği gösterilmiştir.

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ISP: An Optimal Out-of-Core Image-Set Processing Streaming Architecture for Parallel Heterogeneous Systems

Cited by 6 publications

References 42 publications

Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

Heterogeneous hardware accelerator architecture for streaming image processing

Mikro Yapıların Tersine Mühendislik Yöntemleri ile Sonlu Elemanlar Yöntemi Kullanılarak Modellenmesi ve Model Geometrilerinin İncelenmesi - Effect of Micro-CT Resolutions of Voxel Based Model and Analysis Results

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