Is time predictability quantifiable?

Schoeberl, Martin

doi:10.1109/samos.2012.6404196

Cited by 15 publications

(7 citation statements)

References 32 publications

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“…We want processor architectures to have predictable timing but we cannot forget about performance, and more specifically, the worst-case performance. In [6], they argue that time predictability is an interesting, but incomplete property. It is very difficult to quantify predictability.…”

Section: Related Workmentioning

confidence: 99%

“…There are a lot of predictability definitions such as BCET and WCET interval, real WCET/WCET bound quotient, BCET/WCET bound quotient, among others. But, as argued in [6], definitions that use absolute values of WCET and BCET are difficult to use because we cannot actually calculate them. We can calculate upper and lower bounds.…”

Section: Related Workmentioning

confidence: 99%

“…Static analysis suffers complexity and scalability problems, mainly in the hardware modeling side due to the focus on averagecase performance in processor development. To enhance the WCET estimation, there is a considerable number of recent works [4], [5], [6], [7] addressing the problem of building timing predictable computer architectures. General purpose processors developed with average-case performance in mind may imply a non-deterministic behavior due to the use of cache memories, branch prediction, speculative execution and out-of-order pipelines.…”

Section: Introductionmentioning

confidence: 99%

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Investigating a four-issue deterministic VLIW architecture for real-time systems

Starke

Carminati

2015

2015 IEEE 13th International Conference on Industrial Informatics (INDIN)

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The correct functioning of real-time systems depends not only on the logically correct response, but also the time when it is given. This type of application is increasingly present today and the processing demand is such that complex processors are needed. Unfortunately general purpose processors are not well suitable for hard real-time applications due to their non-deterministic behavior caused by the use of cache memories, branch prediction, speculative execution and out-oforder pipelines. The goal of this work is to investigate pipeline performance of VLIW (Very Long Instruction Word) architectures for real-time systems with an in-order pipeline, a direct mapped instruction cache and a scratchpad memory to accelerate data memory. The prototype was implemented in VHDL considering the HP VLIW ST231 ISA. We present quantification of WCET and average-case performance and discuss some of the performance loss on using only pure deterministic design.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Investigating a four-issue deterministic VLIW architecture for real-time systems

Starke

Carminati

2015

2015 IEEE 13th International Conference on Industrial Informatics (INDIN)

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“…Schoeberl has argued that time predictability is not quantifiable but that one can compute the WCET of a task and compare it on different architectures [17]. Being time-predictable is then an interaction between:…”

Section: A the T-crest Projectmentioning

confidence: 99%

A Method Cache for Patmos

Degasperi

Hepp

Puffitsch

et al. 2014

2014 IEEE 17th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing

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For real-time systems we need time-predictable processors. This paper presents a method cache as a time-predictable solution for instruction caching. The method cache caches whole methods (or functions) and simplifies worst-case execution time analysis. We have integrated the method cache in the timepredictable processor Patmos.We evaluate the method cache with a large set of embedded benchmarks. Most benchmarks show a good hit rate for a method cache size in the range between 4 and 16 KB.

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“…However, it might be useful also in a non-Java context. We consider to explore the hardware lock unit within the T-CREST multicore architecture [19], which is built out of VLIW RISC processors [23].…”

Section: Future Workmentioning

confidence: 99%

Chip-multiprocessor hardware locks for safety-critical Java

Strøm

Puffitsch

Schoeberl

2013

Proceedings of the 11th International Workshop on Java Technologies for Real-Time and Embedded Systems

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Accessing shared resources in multicore systems is usually protected by a software locking mechanism, which itself is implemented through atomic operations. This can result in a large synchronization overhead, which, in the context of real-time systems, increases the worst-case execution time and may void a task set's schedulability. In this paper we present a hardware locking mechanism to reduce the synchronization overhead. The solution is implemented for the chip-multiprocessor version of the Java Optimized Processor in the context of safety-critical Java. The implementation is compared to a software solution. The performance and the hardware cost are evaluated.

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Is time predictability quantifiable?

Cited by 15 publications

References 32 publications

Investigating a four-issue deterministic VLIW architecture for real-time systems

Investigating a four-issue deterministic VLIW architecture for real-time systems

A Method Cache for Patmos

Chip-multiprocessor hardware locks for safety-critical Java

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