Chip-multiprocessor hardware locks for safety-critical Java

Concurrency and Computation

2016

Self Cite

A software locking mechanism commonly protects shared resources for multithreaded applications. This mechanism can, especially in chip-multiprocessor systems, result in a large synchronization overhead. For real-time systems in particular, this overhead increases the worst-case execution time and may void a task set's schedulability. This paper presents 2 hardware locking mechanisms to reduce the worst-case time required to acquire and release synchronization locks. These solutions are implemented for the chipmultiprocessor version of the Java Optimized Processor. The 2 hardware locking mechanisms are compared with a software locking solution as well as the original locking system of the processor. The hardware cost and performance are evaluated for all presented locking mechanisms. The performance of the betterperforming hardware locks is comparable with that of the original single global lock when contending for the same lock. When several noncontending locks are used, the hardware locks enable true concurrency for critical sections. Benchmarks show that using the hardware locks yields performance ranging from no worse than the original locks to more than twice their best performance. This improvement can allow a larger number of real-time tasks to be reliably scheduled on a multiprocessor real-time platform.

Section: Use Casementioning

confidence: 99%

“…[4] The new contributions of this paper are 2-fold. [4] The new contributions of this paper are 2-fold.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Hardware locks for a real‐time Java chip multiprocessor

Strøm

Puffitsch

Concurrency and Computation

2016

Self Cite

“…Our first attempt [47] uses a content-addressable memory (CAM) to store the address of an object used as a lock. Whenever a core supplies an object's address it is checked against all existing entries.…”

Section: Multi-core Locking Unitmentioning

confidence: 99%

Certifiable Java for Embedded Systems

Proceedings of the 12th International Workshop on Java Technologies for Real-Time and Embedded Systems

Dalsgaard

Hansen

et al. 2014

Self Cite

The Certifiable Java for Embedded Systems (CJ4ES) project aimed to develop a prototype development environment and platform for safety-critical software for embedded applications. There are three core constituents: A profile of the Java programming language that is tailored for safety-critical applications, a predictable Java processor built with FPGA technology, and an Eclipse based application development environment that binds the profile and the platform together and provides analyses that help to provide evidence that can be used as part of a safety case. This paper summarizes key contributions within these areas during the three-year project period. In the conclusion the overall result of the project is assessed.

“…We explored hardware support for locking in a Java multicore processor [2] with a single global lock and a locking unit in parallel to the single global lock [3]. From that starting point we integrated those two components into the Java locking unit (JLU).…”

mentioning

confidence: 99%

Hardware Locks with Priority Ceiling Emulation for a Java Chip-Multiprocessor

Strøm

2015 IEEE 18th International Symposium on Real-Time Distributed Computing

2015

Self Cite

Abstract-According to the safety-critical Java specification, priority ceiling emulation is a requirement for implementations, as it has preferable properties, such as avoiding priority inversion and being deadlock free on uni-core systems.In this paper we explore our hardware supported implementation of priority ceiling emulation on the multicore Java optimized processor, and compare it to the existing hardware locks on the Java optimized processor.We find that the additional overhead for priority ceiling emulation on a multicore processor is several times higher than simpler, non-premptive locks, mainly due to slow access to shared memory. We also find that PCE is mostly viable with large critical sections.