Invited: Chipyard - An Integrated SoC Research and Implementation Environment

Amid, Alon; Biancolin, David; Gonzalez, Abraham; Grubb, Daniel; Karandikar, Sagar; Liew, Harrison; Magyar, Albert; Mao, Howard; Ou, Albert; Pemberton, Nathan; Rigge, Paul; Colin, Stéphane; Wright, John; Zhao, Jerry; Bachrach, Jonathan; Shao, Sophia; Nikolić, Borivoje; Asanović, Krste

doi:10.1109/dac18072.2020.9218756

Cited by 5 publications

(3 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…An alternative to RTL simulation is prototyping FPGA to validate the proposed system. In this context, we found works [12,[14][15][16][17] that enable the exploration of user-level applications in the designed many-core systems. In contrast, HERO [13] support an OS execution, enabling multitasking.…”

Section: Discussionmentioning

confidence: 99%

“…ANDROMEDA [15] and Uhlendorft et al [17] proposals do not provide the capability to create a heterogeneous system. However, Chipyard [14], and ProNoC [12] offer peripheral support. On the other hand, Chipyard is the only proposal that does not natively support NoCs.…”

Section: Discussionmentioning

confidence: 99%

“…The Authors provide a toolchain that allows optimized compilation for both ISAs (ARM and RISC-V) from the same source code, and a Linux driver to enable the PMCA. Amid et al [14] present Chipyard, a framework for many-core development. It provides parameterizable IPs that can be configured and interconnected to build a complete system.…”

Section: Fpga Platfomsmentioning

confidence: 99%

See 2 more Smart Citations

Chronos-V: A Many-Core High-level Model with Support for Management Techniques

Weber

Zotto

Moraees

2022

Preprint

View full text Add to dashboard Cite

This work presents Chronos-V, a Many-Core System-on-Chip (MCSoC) that adopts abstract hardware modeling, executing the FreeRTOS Operating System (OS) at each processing element (PE). Chronos-V is a heterogeneous architecture with two regions: (i) General Purpose Processing Elements (GPPE), responsible for executing user applications; (ii) peripherals that provide IO capabilities or hardware acceleration to the system. Besides the standard goal of high-level models, design space exploration at early design stages with reduced simulation time, our goal is to advance the state-of-the-art in the MCSoC research field by proposing an architecture with hardware and software support for management techniques. As a case study, we present an ODA (Observe-Decide-Actuate) loop for thermal management, comparing it to a dark silicon patterning mapping in a platform with 196 PEs. Thermal maps show the benefits of using dynamic thermal management in terms of hotspot avoidance and temperature reduction.

show abstract