(Invited) Advanced Dielectrics Targeting 2X DRAM MIM Capacitors

Abstract

Reducing the equivalent oxide thickness below 0.45 nm at low leakage current density of 10 -7 A/cm 2 at ± 1V is required for DRAM MIM capacitors for the 2X node. This can be achieved using a bi-layer stack TiO 2 /Sr rich STO (62%), which is converted into a STO layer having 54% Sr content after crystallization anneal. The impact of TiO 2 content in the initial bi-layer on the grain morphology and electrical properties of the final stack was studied. An optimal TiO 2 thickness range was identified, correlated with the grain size. Ti richer STO results in a larger amount of nanocracks and higher leakage current. The electrode/STO interface is critical in reducing the leakage current. In this regard, Ru has shown improved properties as compared to TiN. Moreover, Sr diffusion into Ru identified by SIMS measurements seems to have a beneficial effect on improving the interface and electrical properties.