Investigation on different ESD protection strategies devoted to 3.3 V RF applications (2 GHz) in a 0.18 μm CMOS process

Richier, C.; Salome, P.; Mabboux, G.; Zaza, I.; Juge, André; Mortini, P.

doi:10.1109/eosesd.2000.890084

Cited by 91 publications

(27 citation statements)

References 10 publications

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“…In this work, the shallow-trench-isolation (STI) diodes are employed due to their high Q value [8] and good ESD robustness under forward-biased condition. Initially, the total ESD capacitance (Cesd) was assumed to be 200 fF, a value sufficient to reach the HBM ESD level of 2kV [9]. The corresponding layout dimension for the ESD diodes to generate the parasitic capacitance of 200 fF can be estimated from the CMOS process parameters with consideration of the both bottom-plate and the side-wall capacitances.…”

Section: B Matching Analysis With Smith Chartmentioning

confidence: 99%

Optimization of broadband RF performance and ESD robustness by -model distributed ESD protection scheme

Ker

Kuo

Hsiao

2006

Journal of Electrostatics

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− Large electrostatic discharge (ESD) protection devices close to the I/O pins, beneficial for ESD protection, have an adverse effect on the performance of broadband RF circuits for impedance mismatch and bandwidth degradation. A new proposed ESD protection structure, π-model distributed ESD (π-DESD) protection circuit, composed of one pair of ESD devices near the I/O pin, the other pair close to the core circuit, and a coplanar waveguide with under-grounded shield (CPWG) connecting these two pairs, can successfully achieve both excellent ESD robustness and good broadband RF performance. Cooperating with the active power-rail ESD clamp circuit, the experimental chip in a 0.25-µm CMOS process can sustain the human-body-model (HBM) ESD stress of 8kV.

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Section: B Matching Analysis With Smith Chartmentioning

confidence: 99%

Optimization of broadband RF performance and ESD robustness by -model distributed ESD protection scheme

Ker

Kuo

Hsiao

2006

Journal of Electrostatics

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“…There are some methods to decrease the parasitic capacitances of ESD protection devices. Connecting diodes in series can efficiently achieve the target [3]. Besides, silicon-controlled rectifier (SCR), which has high ESD level with low parasitic capacitance, is often used [4].…”

Section: Introductionmentioning

confidence: 99%

Design of ESD protection for RF CMOS power amplifier with inductor in matching network

Tsai

Lin

Chu

et al. 2012

2012 IEEE Asia Pacific Conference on Circuits and Systems

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Due to the potential for mass production, CMOS technologies have been widely used to implement radiofrequency integrated circuits (RF ICs). Electrostatic discharge (ESD), which is one of the most important reliability issues in CMOS technologies, must be considered in RF ICs. In this work, an on-chip ESD protection design for RF power amplifier (PA) was presented. The ESD protection design consisted of an inductor in the matching network of PA. The PA with this ESD protection had been designed and fabricated in a 65-nm CMOS process. The ESD-protected PA can sustain over 4-kV humanbody-mode (HBM) ESD stress, while the unprotected PA was degraded after 1-kV HBM ESD stress.

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“…The parasitic capacitance (C ESD ) of ESD protection device certainly contributes capacitive loading to the I/O port, which will induce impedance mismatch, power gain degradation, output power loss, and noise figure degradation. The parasitic capacitance of ESD protection circuits is an important design consideration for RF ICs [4], [5]. To reduce the negative impact of ESD protection circuit on RF circuit performance, waffle-structured layout for ESD protection devices had been studied [6].…”

Section: Introductionmentioning

confidence: 99%

ESD protection design for fully integrated CMOS RF power amplifiers with waffle-structured SCR

Ker

Lin

Meng

2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-Waffle-structured SCR (silicon-controlled rectifier) has been studied as an effective on-chip ESD (electrostatic discharge) protection device for CMOS RF (radio-frequency) circuits. In this work, a novel on-chip ESD protection strategy using the waffle-structured SCR is proposed and co-designed with a CMOS UWB (ultra-wideband) PA (power amplifier). Before ESD stress, the RF performances of the ESD-protected PA have been demonstrated to be as well as that of the unprotected PA. After ESD stress, the unprotected PA was seriously degraded, whereas the ESD-protected PA was keeping the performances well.

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Investigation on different ESD protection strategies devoted to 3.3 V RF applications (2 GHz) in a 0.18 μm CMOS process

Cited by 91 publications

References 10 publications

Optimization of broadband RF performance and ESD robustness by -model distributed ESD protection scheme

Optimization of broadband RF performance and ESD robustness by -model distributed ESD protection scheme

Design of ESD protection for RF CMOS power amplifier with inductor in matching network

ESD protection design for fully integrated CMOS RF power amplifiers with waffle-structured SCR

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