Optimization of broadband RF performance and ESD robustness by -model distributed ESD protection scheme

Abstract

− Large electrostatic discharge (ESD) protection devices close to the I/O pins, beneficial for ESD protection, have an adverse effect on the performance of broadband RF circuits for impedance mismatch and bandwidth degradation. A new proposed ESD protection structure, π-model distributed ESD (π-DESD) protection circuit, composed of one pair of ESD devices near the I/O pin, the other pair close to the core circuit, and a coplanar waveguide with under-grounded shield (CPWG) connecting these two pairs, can successfully achieve both excellent ESD robustness and good broadband RF performance. Cooperating with the active power-rail ESD clamp circuit, the experimental chip in a 0.25-µm CMOS process can sustain the human-body-model (HBM) ESD stress of 8kV.

π-Shape ESD Protection Design for Multi-Gbps High-Speed Circuits in CMOS Technology

“…However, a larger size for protection devices will result in higher parasitic capacitance and lead to extra signal loss. To overcome this issue, ESD protection circuits for high-speed applications are splitting ESD protection circuits into multiple sections [ 16 , 17 ]. This method can hold the ESD robustness and cause lower high-frequency degradation.…”

Capacitance investigation of diodes and SCRs for ESD protection of high frequency circuits in sub-100nm bulk CMOS technologies

“…In extreme cases, ESD performance has to be sacrificed to achieve acceptable circuit performance. Several ESD co-design approaches have been published to partially relax the urgent need for low capacitance and have proved successful [2][3][4][5][6][7][8][9].…”