Investigation of ultra-thin gate oxide reliability behavior by separate characterization of soft breakdown and hard breakdown

Pompl, T.; Wurzer, H.; Kerber, M.; Eisele, I.

doi:10.1109/relphy.2000.843889

Cited by 26 publications

(9 citation statements)

References 22 publications

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“…This view was not consistent with a later statistical analysis of data [176] showing that the distribution of breakdown times is independent of whether they are soft or hard, and that an HBD which occurs after an SBD is a random event uncorrelated with the first SBD spot. It was also shown that SBD and HBD follow similar area dependence [177] but the temperature dependence and voltage dependence were found to be different [178] or the same [179] in different laboratories. The similar light emission spectral characteristics of SBD and HBD [180] also support the idea that they are related phenomena, differing only in the size of the breakdown spot.…”

Section: A Soft Breakdownmentioning

confidence: 96%

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Stathis

2001

IEEE Trans. Device Mater. Relib.

163

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Abstract-The microelectronics industry owes its considerable success largely to the existence of the thermal oxide of silicon. However, recently there is concern that the reliability of ultra-thin dielectrics will limit further scaling to slightly thinner than 2 nm. This paper will review the physics and statistics of dielectric wearout and breakdown in ultrathin SiO 2 -based gate dielectrics. Electrons or holes tunneling through the gate oxide generate defects until a critical density is reached and the oxide breaks down. The critical defect density is explained by the formation of a percolation path of defects across the oxide. Only 1% of these paths ultimately lead to destructive breakdown, and the microscopic nature of these defects is not known. The rate of defect generation decreases approximately exponentially with supply voltage, below a threshold voltage of about 5 V for hot electron-induced hydrogen release. However, the tunnel current also increases exponentially with decreasing oxide thickness, leading to a decreasing time-to-breakdown and a diminishing margin for reliability as device dimensions are scaled. Estimating the reliability of the dielectric requires an extrapolation from the measurement conditions (e.g., higher voltage) to operation conditions. Because of the diminished reliability margin, it has become imperative to try to reduce the error in this extrapolation.Long-term ( 1 year) stress experiments are now being used to measure the wearout and breakdown of ultrathin ( 2 nm) dielectric films as close as possible to operating conditions. These measurements have revealed the details of the voltage dependence of the defect generation rate and critical defect density, allowing better modeling of the voltage dependence of the time-to-breakdown. Such measurements are used to guide the technology development prior to the manufacturing stage. We then discuss the nature of the electrical conduction through a breakdown spot and the effect of the oxide breakdown on device and circuit performance. In some cases, an oxide breakdown does not lead to immediate circuit failure, so more research is needed in order to develop a quantitative methodology for predicting the reliability of circuits.

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Section: A Soft Breakdownmentioning

confidence: 96%

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Stathis

2001

IEEE Trans. Device Mater. Relib.

163

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“…It has been reported that the voltage and temperature acceleration parameters obtained from devices that experienced soft breakdown were different from those obtained from devices that experienced hard breakdown [96], [97]. It was shown by Suñé [98] through statistical analysis that both hard and soft breakdown share a similar origin.…”

Section: A Soft Breakdownmentioning

confidence: 99%

Ultrathin gate oxide reliability: physical models, statistics, and characterization

Suehle

2002

IEEE Trans. Electron Devices

144

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Abstract-The present understanding of wear-out and breakdown in ultrathin ( 5 0 nm) SiO 2 gate dielectric films and issues relating to reliability projection are reviewed in this article. Recent evidence supporting a voltage-driven model for defect generation and breakdown, where energetic tunneling electrons induce defect generation and breakdown will be discussed. The concept of a critical number of defects required to cause breakdown and percolation theory will be used to describe the observed statistical failure distributions for ultrathin gate dielectric breakdown. Recent observations of a voltage dependent voltage acceleration parameter and non-Arrhenius temperature dependence will be presented. The current understanding of soft breakdown will be discussed and proposed techniques for detecting breakdown presented. Finally, the implications of soft breakdown on circuit functionality and the applicability of applying current reliability characterization and analysis techniques to project the reliability of future alternative gate dielectrics will be discussed.

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“…On the other hand, high temperature enhances gate oxide breakdown, which is a strong function of temperature and electric field [17]. In our stress experiments, however, no noticeable increase in gate leakage current was detected when V DD2 was stressed at 3.5, 4, and 4.5 V. This suggests that no transistor oxide hard breakdown occurred since hard breakdown typically results in a sudden surge of gate current [18], [19] and could collapse RF performances. In addition, the ADS circuit simulation indicates that the peak drain-gate voltage of the cascode transistor with the oxide thickness of 4.08 nm results in a smaller electric field than the critical field for oxide breakdown [20].…”

Section: Physical Insight Through the Mixed-mode Device And Circumentioning

confidence: 52%

Experimental Verification of RF Stress Effect on Cascode Class-E PA Performance and Reliability

Yuan

Yen

Chen

et al. 2012

IEEE Trans. Device Mater. Relib.

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Abstract-A cascode class-E power amplifier (PA) operating at 5.2 GHz has been designed using Advanced Design System simulation. RF circuit performances such as output power and power-added efficiency before and after RF stress have been experimentally investigated. The measured output power, power-added efficiency, and linearity after high-input-power RF stress at elevated supply voltage show significant circuit degradations. The impact of hot-carrier injection and gate oxide soft breakdown on cascode class-E PA reliability is discussed.Index Terms-Cascode class E, gate oxide breakdown, output power, power amplifier (PA), power efficiency, reliability.

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Investigation of ultra-thin gate oxide reliability behavior by separate characterization of soft breakdown and hard breakdown

Cited by 26 publications

References 22 publications

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Ultrathin gate oxide reliability: physical models, statistics, and characterization

Experimental Verification of RF Stress Effect on Cascode Class-E PA Performance and Reliability

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