Investigation of Trenched and High Temperature Annealed 4H-SiC

Abstract

This study focuses on the effects of a high temperature anneal after dry etching of trenches (post-trench anneal, PTA) on 4Hsilicon carbide (4H-SiC). We aim at the optimum 4H-SiC post-trench treatment with respect to the fabrication and the operation of a trenched gate metal oxide semiconductor field effect transistor (Trench-MOSFET). PTA significantly reduces micro-trenches, also called sub-trenches [, in the corners of the bottom of the trench. This is highly beneficial in case the etched trench sidewall is used as the channel of a Trench-MOSFET. However, PTA is also shown to cause a slight enlargement of the trench width along with a considerable increase of the substrate surface roughness. In addition, X-ray photoelectron spectroscopy (XPS) depth profiles indicate an increased carbon atom concentration at the 4H-SiC surface after the high temperature PTA. The non-stoichiometric surface composition affects the quasi-static capacitance-voltage (QSCV) behavior of MOS structures using a deposited gate oxide (GOX). We assume that a sacrificial oxidation directly after the PTA could restore a stoichiometric 4H-SiC surface.

Impact of Post-Trench Processing on the Electrical Characteristics of 4H-SiC Trench-MOS Structures with Thick Top and Bottom Oxides

“…It is assumed that etching defects are not sufficiently annealed using the 'low anneal temperature' during the PTP, which goes along with minor smoothed etch profiles. By contrast, edges at the upper and at the lower part of the trenched sidewalls are rounded distinctly if a 'high anneal temperature' is used [3], see Fig. 2.…”

“…Furthermore, it is shown that an inert gas anneal, either performed at low temperature or at high temperature, accounts for a low quality MOS interface as the transition region between accumulation and depletion is stretched out. It is assumed that these depletion phenomena originate from a near-surface excess of carbon due to the sublimation of Si atoms during the high temperature anneal process [3,5]. Fig.…”