Impact of Post-Trench Processing on the Electrical Characteristics of 4H-SiC Trench-MOS Structures with Thick Top and Bottom Oxides

Abstract

This study focuses on the evaluation of different post-trench processes (PTPs) for Trench-MOSFETs. Thereto, two different types of inert gas anneals at process temperatures above 1250 °C are compared to a sacrificial oxidation as PTP. The fabricated 4H-SiC Trench-MOS structures feature a thick silicon dioxide (SiO2) both at the wafer surface (‘top’) and in the bottom of the trenches (‘bottom’) in order to characterize only the thin gate oxide at the trenched sidewalls. It is shown that an inert gas anneal at a process temperature between 1400 °C and 1550 °C yields uniform current/electric field strength (IE) values and excellent dielectric breakdown field strengths up to 12 MV/cm using a SiO2 gate oxide of approximately 40 nm thickness. Charge-to-breakdown (QBD) measurements at a temperature T of 200 °C confirm the necessity of a high temperature inert gas anneal after 4H-SiC trench etching in order to fabricate reliable Trench-MOS devices. QBD values up to 16.2 C/cm² have been measured at trenched and high temperature annealed sidewalls, which is about twice the measured maximum QBD value of the corresponding planar reference MOS structure. The capacitive MOS interface characterization points out the need for a sacrificial oxidation subsequent to a high temperature inert gas anneal in order to ensure a high quality MOS interface with excellent electrical properties.

An extraction method of channel resistance for analysis of carrier scattering mechanism in SiC trench MOSFETs

“…3) Many studies have recently demonstrated that trench MOSFETs have a relatively small specific on-resistance (R on A). [4][5][6][7][8][9][10][11][12][13][14][15][16][17][18] However, the reported field-effect channel mobility values of trench MOSFETs are in the range of 5-50 cm 2 V −1 s −1 , which is smaller than those of lateraltype MOSFETs using the same crystal phase (m-face or aface) for a channel. 3) In addition, since the trench sidewall that is the channel region of MOSFETs is difficult to evaluate, the mechanism that limits the channel mobility in trench MOSFETs is unclear.…”

Effect of surface roughness of trench sidewalls on electrical properties in 4H-SiC trench MOSFETs

“…5) In fact, many reports have demonstrated several types of trench MOSFETs with relatively small specific-on-resistance (R on A) values. 3,[6][7][8][9][10][11][12][13][14][15][16][17] However, the use of trench MOSFETs still has challenges. One of the challenges is a channel mobility lower than that expected from lateral MOSFETs.…”

Trench-MOSFETs on 4H-SiC

“…These improvements with respect to conventional silicon-based PCUs originate from the paramount material properties of 4H-SiC like the large band gap and the high thermal conductivity as well as the high integration density of trenched-gate devices. Moreover, it was shown that etched 4H-SiC sidewalls are well suited for the fabrication of highly robust gate dielectrics [2,3], which has always been one of the major challenges in 4H-SiC MOS technology.…”