Investigation of the Off-State Degradation in Advanced FinFET Technology—Part II: Compact Aging Model and Impact on Circuits

Sun, Zixuan; Wang, Runsheng; Zhang, Lining; Zhang, Jiayang; Zhang, Zuodong; Song, Jiahao; Wang, Da; Ji, Zhigang; Huang, Ru

doi:10.1109/ted.2023.3239587

Cited by 3 publications

(5 citation statements)

References 34 publications

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“…This degradation phenomenon is explained as secondary carriers being captured by traps near the drain region, causing a decrease in effective channel length, resulting in reduced threshold voltage and an increase in leakage current. However, in advanced FinFETs, off-state degradation is considered a complex phenomenon involving multiple electrical traps and mechanisms [ 100 , 101 ]. As shown in Figure 11 , the non-monotonic shift of threshold voltage caused by the contribution of multiple electrical traps has been observed in FinFETs.…”

Section: Mixed-mode Reliability Mechanismsmentioning

confidence: 99%

“…The degradation phenomenon observed when the device is under the bias condition of |V gs | > 0 V, |V ds | > 0 V is referred to as hot carrier degradation (HCD) [ 34 , 35 , 36 , 37 , 38 , 39 , 40 , 41 ]. The degradation observed under the bias condition of V gs = 0 V, |V ds | > 0 V is termed off-state degradation (OSD) [ 42 , 43 , 44 ]. Meanwhile, during device operation, the devices also face failure issues such as time-dependent dielectric breakdown (TDDB) [ 45 , 46 , 47 ] and electromigration (EM) [ 48 , 49 , 50 ].…”

Section: Introductionmentioning

confidence: 99%

“…Micromachines 2024, 15, x FOR PEER REVIEW 2 of 22 observed under the bias condition of Vgs = 0 V, |Vds| > 0 V is termed off-state degradation (OSD) [42][43][44]. Meanwhile, during device operation, the devices also face failure issues such as time-dependent dielectric breakdown (TDDB) [45][46][47] and electromigration (EM) [48][49][50].…”

Section: Introductionmentioning

confidence: 99%

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The Understanding and Compact Modeling of Reliability in Modern Metal–Oxide–Semiconductor Field-Effect Transistors: From Single-Mode to Mixed-Mode Mechanisms

Sun,

Chen,

Zhang

et al. 2024

Micromachines

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With the technological scaling of metal–oxide–semiconductor field-effect transistors (MOSFETs) and the scarcity of circuit design margins, the characteristics of device reliability have garnered widespread attention. Traditional single-mode reliability mechanisms and modeling are less sufficient to meet the demands of resilient circuit designs. Mixed-mode reliability mechanisms and modeling have become a focal point of future designs for reliability. This paper reviews the mechanisms and compact aging models of mixed-mode reliability. The mechanism and modeling method of mixed-mode reliability are discussed, including hot carrier degradation (HCD) with self-heating effect, mixed-mode aging of HCD and Bias Temperature Instability (BTI), off-state degradation (OSD), on-state time-dependent dielectric breakdown (TDDB), and metal electromigration (EM). The impact of alternating HCD-BTI stress conditions is also discussed. The results indicate that single-mode reliability analysis is insufficient for predicting the lifetime of advanced technology and circuits and provides guidance for future mixed-mode reliability analysis and modeling.

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Section: Mixed-mode Reliability Mechanismsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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The Understanding and Compact Modeling of Reliability in Modern Metal–Oxide–Semiconductor Field-Effect Transistors: From Single-Mode to Mixed-Mode Mechanisms

Sun,

Chen,

Zhang

et al. 2024

Micromachines

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“…For BTI modelling, the stress temperature of the transistor is generally 125 °C [ 18 , 20 , 21 , 22 ]. Under these extreme conditions and for just a few hours of measurement, the average degradation measured is between 3–8% and corresponds to the degradation predicted for three years of use under operational conditions, which represents an acceleration factor of around 2000 [ 17 ]. Applying such high stresses can result in the occurrence of failure mechanisms which are not representative of those present under operational conditions.…”

Section: Introductionmentioning

confidence: 99%

“…It is expensive to monopolise such a test bench with access to the transistor, so most of the degradation measurements are carried out for less than 10,000 s (≈3 h) [ 10 , 12 , 16 , 17 ]. In order to observe degradation over a short test period, the ageing conditions applied are far from operational conditions.…”

Section: Introductionmentioning

confidence: 99%

Degradation Measurement and Modelling under Ageing in a 16 nm FinFET FPGA

Sobas,

Marc

2023

Micromachines

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Most of the latest generation of integrated circuits use FinFET transistors for their performance, but what about their reliability? Does the architectural evolution from planar MOSFET to FinFET transistor have any effect on the integrated circuit reliability? In this article, we present a test bench we have developed to age and measure the degradation of 5103 ring oscillators (ROs) implemented in nine FPGAs with 16nm FinFET under different temperature and voltage conditions (Vnom≤Vstress≤1.3Vnom and 25°C≤Tstress≤115°C) close to operational conditions in order to predict reliability regarding degradation mechanisms at the transistor scale (BTI, HCI and TDDB) as realistically as possible. By comparing our initial RO measurements and the data extracted from Vivado, we will show that the performance of the nine FPGAs is between 50% and 70% of the best performance expected by Vivado. After 8000 h of ageing, we will see that the relative degradations of the RO are a maximum of 1%, which is a first indicator proving the FPGAs’ good reliability. By comparing our results with similar studies on 28 nm MOSFET FPGAs, we will reveal that 16 nm FinFET FPGAs are more reliable. To be implemented in an FPGA, an RO uses logic resources (LUT) and routing resources. We will show that degradation in the two types of resources is different. For this reason, we will present a method for separating degradations in logical and routing resources based on RO degradation measures. Finally, we will model rising and falling edge propagation time degradations in an FPGA as a function of time, temperature, voltage, signal duty cycle and resources used in the FPGA.

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A Device-Circuit Aging Simulation Framework Integrating Trap-Based Models and Sensitivity Analysis for FinFET Technology

Li,

Xue,

Sun

et al. 2024

IEEE Trans. Electron Devices

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Investigation of the Off-State Degradation in Advanced FinFET Technology—Part II: Compact Aging Model and Impact on Circuits

Cited by 3 publications

References 34 publications

The Understanding and Compact Modeling of Reliability in Modern Metal–Oxide–Semiconductor Field-Effect Transistors: From Single-Mode to Mixed-Mode Mechanisms

The Understanding and Compact Modeling of Reliability in Modern Metal–Oxide–Semiconductor Field-Effect Transistors: From Single-Mode to Mixed-Mode Mechanisms

Degradation Measurement and Modelling under Ageing in a 16 nm FinFET FPGA

A Device-Circuit Aging Simulation Framework Integrating Trap-Based Models and Sensitivity Analysis for FinFET Technology

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