Investigation of Si/4H-SiC Hetero-Junction Growth and Electrical Properties

Guy, Owen J.; Pérez‐Tomás, Amador; Jennings, Michael R.; Lodzinski, Michal; Castaing, A.; Mawby, P.A.; Covington, James A.; Wilks, S.P.; Hammond, R.; Connolly, D. J.; Jones, S.; Hopkins, James F.; Wilby, Tony; Rimmer, N.; Baker, Karl W.; Conway, S.; Evans, Sarah R.

doi:10.4028/www.scientific.net/msf.615-617.443

Cited by 8 publications

(6 citation statements)

References 6 publications

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“…The magnitudes of the currents for reverse-bias voltages of these junctions are equal to each other at each temperature. It is notable that the magnitude of the reverse-bias currents measured at 27 °C is lower than those previously measured at room temperature for n-Si/n-SiC 8) and p-Si/n-SiC 24) junctions fabricated by other methods. The reverse-bias current increases by ³10 5 times as the measurement temperature increases to 200 °C.…”

Section: Current-voltage Characteristicscontrasting

confidence: 66%

Correlation between the electrical properties of p-Si/n-4H-SiC junctions and concentrations of acceptors in Si

Nishida

Liang

Hayashi

et al. 2015

Jpn. J. Appl. Phys.

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We fabricated p + -, p-, and p % -Si/n-4H-SiC junctions by surface activated bonding (SAB). We investigated their electrical properties by measuring their current-voltage (I-V) characteristics at raised ambient temperatures, capacitance-voltage (C-V) characteristics at various frequencies, and capacitance-frequency (C -f ) characteristics at room temperature. The activation energy of their reverse-bias current and the flat-band voltage in their C-V characteristics, which were estimated to be 0.97-1.01 eV and 0.83-0.84 V, respectively, were insensitive to the concentrations of acceptors in Si substrates. The relaxation times estimated from the C-f characteristics were 0.8 and 1.5 µs for the p-Si/n-4H-SiC and p % -Si/n-4H-SiC junctions, respectively. The results are explained by a scheme wherein Fermi level pinning occurs at the Si/4H-SiC interfaces fabricated by SAB.

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Section: Current-voltage Characteristicscontrasting

confidence: 66%

Correlation between the electrical properties of p-Si/n-4H-SiC junctions and concentrations of acceptors in Si

Nishida

Liang

Hayashi

et al. 2015

Jpn. J. Appl. Phys.

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“…Some technology should be adopted to maintain the quality of Si/SiC heterojunction. The studies about epitaxy of Si/SiC thin films have previously been made [13, 14]. Although the isostructural lattices of Si and 4H‐SiC present a high mismatch that leads to a strain induced surface roughening of the Si layer during growth, Si atoms would preferentially incorporate in the peaks as this is energetically favourable for the partial relaxation of the lateral strain [15].…”

Section: Device Structure and Simulationmentioning

confidence: 99%

Negative bias temperature instability in SOI‐like p‐type metal oxide semiconductor devices

Shan

Wang

et al. 2018

Micro & Nano Letters

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A silicon on insulator (SOI)-like bulk silicon (SLBS) MOSFET has been recently reported. An 'n/p-/n+' structure was contained in SLBS P Metal Oxide Semiconductor (PMOS) device, with 'p-' is made of 4H-SiC. This player is fully depleted. In this work, negative bias temperature instability (NBTI) of SLBS pMOSFET is studied and compared with that in bulk and Fully Depleted (FD) SOI PMOSFET. The effects of stress temperature and body bias on NBTI of SLBS device are also be studied in this work. The work demonstrates an advantage of SLBS over bulk and FD SOI devices.

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“…This is the most important issue limiting the feasibility of production of real N–SL–BS devices. The epitaxy of Si/SiC thin films with a p/n–/p + structure has previously been studied [10, 11]. Although the isostructural lattices of Si and 4H‐SiC present a high lattice mismatch that leads to a strain‐induced surface roughening of the Si layer during growth, Si atoms would preferentially incorporate in the peaks as this is energetically favourable, leading to the partial relaxation of the lateral strain [12].…”

Section: Simulation Of Device and Basic Characteristicmentioning

confidence: 99%

Reliability improvements in SOI‐like MOSFET with ESD and self‐heating effect

Cao

Shan

Wang

et al. 2018

Micro & Nano Letters

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A new structure of N-type Silicon-on-insulator (SOI)-Like Bulk Silicon (N-SL-BS) metal-oxide-semiconductor field-effect transistor (MOSFET) is proposed to improve the reliability of SOI MOSFET mainly with regards to their self-heating effect and electro-static discharge (ESD) events based on two-dimensional numerical simulation. The new device employs p/n-/p + structure on Si, in which the n-layer is made of Si carbide (SiC), a wide bandgap material. The built-in electric field fully depletes the n-SiC layer and forms an SOI-like feature with a p + layer underneath. Simulations are first implemented in self-heating conditions, to investigate their drain current and temperature ramping. More importantly, ESD pulses assuming the human body model are applied to test their response and observe which device was first to fail using an I-V curve and hole current density distribution. Results show that the new device exhibits superior reliability when compared with a traditional SOI MOSFET. The avalanche breakdown voltage improves nearly 33% and the highest temperature of the global device is more than three times lower than that of an SOI MOSFET subjected to ESD pulses with a peak current of 7 mA.

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Investigation of Si/4H-SiC Hetero-Junction Growth and Electrical Properties

Cited by 8 publications

References 6 publications

Correlation between the electrical properties of p-Si/n-4H-SiC junctions and concentrations of acceptors in Si

Correlation between the electrical properties of p-Si/n-4H-SiC junctions and concentrations of acceptors in Si

Negative bias temperature instability in SOI‐like p‐type metal oxide semiconductor devices

Reliability improvements in SOI‐like MOSFET with ESD and self‐heating effect

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