Investigation of oxidation-induced strain in a top-down Si nanowire platform

Abstract

a b s t r a c tIn this paper, we investigate the effect of different process parameters on oxidation-induced strain (OIS) into a doubly-clamped silicon nanowire FET to control and finally, enhance carrier mobility. Spacer technology together with sacrificial thermal oxidation were used to fabricate %100 nm wide Si NWs. The built-in tensile stress in the Si NWs was measured using micro-Raman spectroscopy and a maximum of 2.6 GPa was found.

Accumulation-mode GAA Si NW nFET with sub-5 nm cross-section and high uniaxial tensile strain

“…In this paper, we represent a fabrication process to make deeply scaled highly doped sub-5 nm Si nanowires from a top-down SOI platform and integrate it with the local stress platforms, local oxidation [4] and metal-gate strain [5], to include ≥ 2.5 GPa uniaxial tensile stress in the channel to boost the carrier mobility in highly doped AMOSFETs, without affecting the I ON /I OF F value.…”

“…2). To reduce the Fin width even below 10 nm, round the sharp Si corners as well as accumulate uniaxial tensile stress in the suspended Si nanowire [4], a 7 hour stress-limited dry oxidation at 925…”

Accumulation-mode gate-all-around si nanowire nMOSFETs with sub-5nm cross-section and high uniaxial tensile strain

“…In this paper, we represent a fabrication process to make deeply scaled highly doped sub-5 nm Si nanowires from a top-down SOI platform and integrate it with the local stress platforms, local oxidation [5] and metal-gate strain [6], to include P2.5 GPa uniaxial tensile stress in the channel to boost the carrier mobility in highly doped AMOSFETs, without affecting the I ON /I OFF value.…”

“…2). To reduce the Fin width even below 10 nm, round the sharp Si corners as well as accumulate uniaxial tensile stress in the suspended Si nanowire [5], a 7 h stress-limited dry oxidation at 925°C (0.500 L/min O 2 , 10.00 L/min N 2 ), to consume nominally 9 nm of (1 0 0) Si, in the presence of the tensile nitride hard mask was done. It is worth mentioning that the Si consumption on the slanted Si side-walls was observed to be %40% higher than (1 0 0) Si surface.…”

“…Afterward, RCA (including 8 min HF dip to strip the grown SiO 2 and suspend the Si nanowires from the substrate), 5 finally, 50 nm TiN deposition by sputtering including intrinsic compressive thin film stress were done to make the gate stack as well as accumulate more uniaxial tensile stress in the suspended Si nanowires [6].…”