Investigation of local charged defects within high-temperature annealed HfSiON∕SiO2 gate stacks by scanning capacitance spectroscopy

Abstract

We studied the oxide charges and traps within nitrided Hf-silicate (HfSiON)∕SiO2 gate stacks processed with high-temperature annealing with a spectroscopic technique by using high spatial resolution scanning capacitance microscopy. Spectroscopy was performed by detecting the static capacitance (dC∕dZ) between a conductive probe and the sample while sweeping the sample bias. The dC∕dZ image and spatially resolved dC∕dZ-V spectrum revealed the existence of positive fixed charges within HfSiON and interface trap charges between the SiO2 underlayer and Si substrate. We also observed a transient electron trap process from the conductive probe to the HfSiON film as abrupt discontinuities in the dC∕dZ-V spectrum and with bias-induced topography change of the HfSiON surface. These oxide charges and trap sites distribute inhomogeneously within HfSiON∕SiO2 gate stacks, and the origin of these charged defects is ascribable to phase separation induced by high-temperature postdeposition annealing.

Scanning capacitance microscopy study of carrier depletion within grains of n‐type polycrystalline silicon

“…[4] The detailed explanation of our SCM is described elsewhere. [5,6] Fig. 1 is a schematic that illustrates the basic setup used for SCM measurement in this study.…”

“…Using dC/dZ imaging, we were able to observe the cross-sectional structure of semiconductor devices [5] and the fixed charges within high-k films. [6] The electrical contact between the poly-Si layer and the SCM sample holder was secured with silver epoxy paste. The d.c. sample bias (V dc ) was supplied to the poly-Si layer while the SCM probe was grounded through the capacitance sensor.…”

Study on channel depletion in metal‐oxide‐semiconductor field effect transistor using top‐view imaging through scanning capacitance microscopy

“…With the use of dC/dZ imaging, we assessed the trapped charges within dielectric films. [11,13] For SCM measurements, electrical contact with the sample backplane was made with silver epoxy glue on the SCM sample holder. An AC modulation bias (V ac ) for dC/dV imaging and/or a DC offset bias (V dc )s was supplied to the sample while the SCM probe was grounded through the capacitance sensor.…”

“…[8,9] Therefore, instead of using the traditional optical deflection method and a metal-coated Si cantilever, we have used a quartz oscillator as a high-sensitive force sensor and sharpened tungsten wire as a conductive probe for SCM. [10,11] In the present study, we demonstrated our SCM application to evaluate carrier profiling within a MOSFET channel and discussed its dependence on the L g when top-view imaging using dC/dZ measurement is used.…”

Investigation of nonuniformity phenomenon in nanoscale SiO2 and high-k gate dielectrics

“…10,11 It has been reported that the local depletion capacitance with deeper depletion width triggered by local oxide charges had been practically visualized by scanning capacitance microscopy. 12,13 In addition, the lateral nonuniformity of oxide charge in ultrathin gate dielectrics had been also characterized. 1,2 However, the studies of nonuniformity from D.D.…”