Investigation of Geometry Dependence of Thermal Resistance and Capacitance in RF SOI MOSFETs

Chen, Zhanfei; Sun, Lingling; Li, Jun; Su, Guodong; Zhou, Wenyong

doi:10.1109/ted.2018.2863022

Cited by 8 publications

(9 citation statements)

References 21 publications

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“…7 the total gate width and substrate temperature, respectively, were previously obtained in [6] and [19]. Furthermore, thermal capacitances of the same order of magnitude (0.1-5×10 −9 J/°C) were measured in [6] for RF SOI-MOSFETs and [24] for FinFETs.…”

Section: B Modelingmentioning

confidence: 70%

“…Finally, it can be highlighted that confinement due to gate length scaling results in smaller thermal capacitances; a linear dependency of the thermal capacitance on channel length is also expected [6]. In this scenario, as (4) indicates, the increment observed for ∆gddT when the gate length is reduced [25], is balanced with a superior drain current, resulting on a constant minimum thermal capacitance (maximum thermal resistance [26]) for ultra-short devices, when extrinsic elements determine the device thermal performance (as contacts do not scale with gate length).…”

Section: B Modelingmentioning

confidence: 99%

“…Small-signal equivalent circuit analysis has been used for investigating heat flow paths in SOI-MOSFETs [18]. Nevertheless, empirical approaches are needed, such as fitting of the elements of the electrical/thermal circuit or the use of multiple-pole RC networks for the thermal part [6], [15]. Other studies are based on the transient response to pulsed measurements and the determination of the thermal time constant, τth (τth = RthCth) [19].…”

mentioning

confidence: 99%

“…In addition, a model for the thermal capacitance is proposed, to be implemented in circuit simulators, which is valid when the thermal coupling increases by the use of multi-finger devices [12], and that includes the substrate temperature and total gate width dependencies. Regarding the channel length, it has an impact that is less significant on SOI-MOSFET self-heating than compared to channel width, as usually the change of channel width is much greater than that of channel length [6].…”

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confidence: 99%

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Temperature-Dependent Thermal Capacitance Characterization for SOI-MOSFETs

González

Aja

Artal

et al. 2019

IEEE Trans. Electron Devices

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Thermal capacitances are required to describe fast dynamic thermal behavior in SOI devices. This paper presents a physical model based on the AC technique, together with the characteristic thermal frequency determination through the frequency response of the output conductance, for calculating the thermal capacitance of single-finger and multi-finger SOI-MOSFETs. The model accounts for total gate width and substrate temperature, making evident the augmented thermal coupling when multi-fingers are used. Thermal capacitances and corresponding time constants, extracted from a variety of gate widths and number of fingers, are correctly predicted up to a substrate temperature of 150°C. Index Terms-electrothermal characterization, model, SOI-MOSFET, substrate temperature, thermal capacitance. I. INTRODUCTION ilicon-on-insulator (SOI) MOSFETs, having a buried oxide layer thicker than 100 nm, suffer from obstruction of the heat flow towards the substrate [1], [2]. This, together with the ultra-thin internal layers used at nanometer length scales, with a reduced thermal conductivity [3], [4], results in a remarkable self-heating effect, particularly in DC operation/biasing with relevant electrical power levels involved (as from dozens of mW [5]). This makes the design and configuration of terminals, acting as heat sinks, critical in SOI-MOSFET performance [1], [6]. The typical thermal model for the temperature rise in devices, induced by self-heating effects, consists of the equivalent circuit shown in Fig. 1, with the thermal resistance, Rth, and capacitance, Cth, being connected in parallel. This model is based on the following analogy between electrical

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Section: B Modelingmentioning

confidence: 70%

Section: B Modelingmentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

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Temperature-Dependent Thermal Capacitance Characterization for SOI-MOSFETs

González

Aja

Artal

et al. 2019

IEEE Trans. Electron Devices

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“…The gate width is usually the only geometrical parameter considered during the thermal modeling of SOI MOS-FETs [4], [9]. However, it has been demonstrated that the length of the channel has a non-negligible impact on the thermal impedance [10] and must be considered for precise compact modeling [11].…”

mentioning

confidence: 99%

Gate Length-Dependent Thermal Impedance Characterization of PD-SOI MOSFETs

González

Cabrera

Lázaro

2022

IEEE Trans. Electron Devices

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Thermal impedance is required to describe static and fast dynamic thermal behavior in silicon-oninsulator (SOI) devices. This study presents an empirical physical model, which accounts for gate length, for calculating the thermal impedance of multi-finger partially depleted (PD) SOI MOSFETs at room temperature. For the first time, the parameters of the model are obtained from measurements of ac conductance and the characteristic thermal frequency determination. The model shows decreasing thermal resistance and linearly augmented thermal capacitance with increasing gate length from 0.18 to 2.50 μm. Thus, thermal time constants of ∼760 ns, extracted from a variety of gate lengths, are correctly predicted.

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Experimental study and signal analysis of acoustic emission from power MOSFET

Zou

Zhang

et al. 2021

Microelectronics Reliability

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Investigation of Geometry Dependence of Thermal Resistance and Capacitance in RF SOI MOSFETs

Cited by 8 publications

References 21 publications

Temperature-Dependent Thermal Capacitance Characterization for SOI-MOSFETs

Temperature-Dependent Thermal Capacitance Characterization for SOI-MOSFETs

Gate Length-Dependent Thermal Impedance Characterization of PD-SOI MOSFETs

Experimental study and signal analysis of acoustic emission from power MOSFET

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