Investigation of Gate Length Effect on SOI-MOSFET Operation

Hosseini, Seyed Ebrahim; Anvarifard, Mohammad K.; Rahmani, Abolfazle; Armaki, Mahdi Gordi

doi:10.1109/icsps.2009.173

Cited by 2 publications

(2 citation statements)

References 7 publications

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“…Higher drain current is required for Analog/RF applications, CASE-1 shows a great uniformity and large value as compared to CASE-2 and CASE-3 and hence an improvement in the device current. Drain voltage's effect on current is less than outing resistant of increase in transistor [32].…”

Section: Resultsmentioning

confidence: 96%

Traps induced Greens function based mathematical modeling for BaTiO₃–SrTiO₃ gate stack dual metal GAA MOSFET

Gauba¹,

Pratap²,

Rewari³

et al. 2019

Semicond. Sci. Technol.

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In this paper, an analytical model has been developed to analyze the impact of trap charges on Dual Metal Gate-All-Around (DMGAA) MOSFET with BaTiO 3 -SrTiO 3 epitaxial oxide layer as gate stack using Greens function and conformal mapping. Trap charges have been induced to observe the changes in surface potential, electric field and drain current. To further investigate the impact of trap charges the trap density is varied. This enhances the drain current with high I ON /I OFF ratio. The analytical results so obtained are compared with the simulated data and are in good agreement thus validating the proposed model. It is also proposed that the device can offer high performance, low leakage power along with high gain and is perfect for analog RF applications. It can be concluded that proposed DMGAA MOSFET is a promising device and a suitable replacement for the existing conventional GAA MOSFETs.

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Section: Resultsmentioning

confidence: 96%

Traps induced Greens function based mathematical modeling for BaTiO₃–SrTiO₃ gate stack dual metal GAA MOSFET

Gauba¹,

Pratap²,

Rewari³

et al. 2019

Semicond. Sci. Technol.

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show abstract

“…g d is used to characterize the device's output resistance (R out = 1/ g d ). 43 I ds & g d increments at +ve ITC is because of mobility enhancement for carriers in the channel region.…”

Section: Resultsmentioning

confidence: 99%

Impact of Interface Trap Charges on Silicon Carbide (4H-SiC) Based Gate – Stack, Dual Metal, Surrounding Gate, FET (4H-SiC- GSDM-SGFET) for Analog and Noise Performance Analysis for 5 G/LTE Applications

Neeraj,

Sharma,

Goel

et al. 2024

ECS J. Solid State Sci. Technol.

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This article examines the impact of various interface trap charges on silicon carbide-based gate – stack, dual metal, surrounding gate, FET (4H-SiC-GSDM-SGFET). It has been contrasted for performance with silicon carbide (4H-SiC)-based dual metal, surrounding gate, FET (4H-SiC-DM- SGFET). For both devices, output characteristics including transconductance (gm), output conductance (gd), drain current (Ids), gate capacitance (Cgg), cutoff frequency (fT) and threshold voltage (Vth) have been examined. Surface potential and electron concentration were also inspected using a contour plot for both the device structures. A gate-stack with a high k- dielectric, Lanthanum oxide (La2O3) along with gate dielectric layer Aluminum oxide (Al2O3) was used for proposed structure implementation. Additionally, we investigated how trap charges affect noise figure (NF) and noise conductance (NC). Also, a CMOS inverter has been developed and its output characteristics have been compared for both the device architectures. ATLAS 3-D device simulator has been employed to conduct the simulations.

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Investigation of Gate Length Effect on SOI-MOSFET Operation

Cited by 2 publications

References 7 publications

Traps induced Greens function based mathematical modeling for BaTiO₃–SrTiO₃ gate stack dual metal GAA MOSFET

Traps induced Greens function based mathematical modeling for BaTiO₃–SrTiO₃ gate stack dual metal GAA MOSFET

Impact of Interface Trap Charges on Silicon Carbide (4H-SiC) Based Gate – Stack, Dual Metal, Surrounding Gate, FET (4H-SiC- GSDM-SGFET) for Analog and Noise Performance Analysis for 5 G/LTE Applications

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Investigation of Gate Length Effect on SOI-MOSFET Operation

Cited by 2 publications

References 7 publications

Traps induced Greens function based mathematical modeling for BaTiO3–SrTiO3 gate stack dual metal GAA MOSFET

Traps induced Greens function based mathematical modeling for BaTiO3–SrTiO3 gate stack dual metal GAA MOSFET

Impact of Interface Trap Charges on Silicon Carbide (4H-SiC) Based Gate – Stack, Dual Metal, Surrounding Gate, FET (4H-SiC- GSDM-SGFET) for Analog and Noise Performance Analysis for 5 G/LTE Applications

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Traps induced Greens function based mathematical modeling for BaTiO₃–SrTiO₃ gate stack dual metal GAA MOSFET

Traps induced Greens function based mathematical modeling for BaTiO₃–SrTiO₃ gate stack dual metal GAA MOSFET