Investigating Effect of Postannealing Time on Positive Bias Stress Stability of In–Ga–Zn–O TFT by Conductance Method

Abstract

The conductance method was used to investigate the positive bias stress (PBS) degradation mechanism of In-Ga-Zn-O (IGZO) thin-film transistor (TFT). The effects of postannealing time on the PBS degradation mechanism were investigated. The stabilization of the donorlike interface defects was found to be the reason for the threshold voltage instability in the IGZO-TFT under the PBS test. The donorlike defects at the front channel interface and in the plasma-enhanced chemical vapor deposition (PE-CVD) SiO x acted as the electron trapping centers. The electron trapping resistance of the PE-CVD SiO x was improved by increasing the postannealing time, resulting in an improvement in the PBS stability. However, long-time postannealing-induced creation of the deep acceptorlike interface defects in the TFT under the PBS. The energy distribution of the created deep acceptorlike interface defects was revealed using the conductance measurement. Index Terms-Acceptorlike interface defects, amorphous In-Ga-Zn-O (IGZO), conductance method, donorlike interface defects, IGZO/SiO x interface, improve positive bias stress (PBS) stability, PBS, positive gate bias stress, thin-film transistor (TFT).

Electrical Stability Modeling Based on Surface Potential for a-InGaZnO TFTs under Positive-Bias Stress and Light Illumination

“…where L is the channel length, and ϕ sd and ϕ ss are the value of ϕ s when V ch = V DS and V ch = 0 V, respectively. In Equation (11), the integral result of Q i (ϕ s ) can be written as…”

“…Although the bandtail states and localized deep states are considered in these models for a-IGZO TFTs, the localized sub-gap density of states (DOSs) is invaluable in solving the model. Actually, new defects are generated in the device channel or at the a-IGZO/gate dielectric interface under external stress conditions [10,11]. For example, it has been demonstrated that the oxygen interstitial (O i )-related defects are created in the device channel or the interface region under gate bias stress, originating from weakly bonded oxygen ions in a-IGZO TFTs [12,13].…”