Introduction to implementation of real time video compression method

Fryza, Tomáš

doi:10.1109/iwssip.2008.4604406

Cited by 4 publications

(7 citation statements)

References 4 publications

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“…These results are compliant with an integration of the 3D DCT/IDCT codec in embedded devices and battery-powered mobile terminal to enable real-time and low-power interactive video functionalities (using encoder and decoder). Particularly the power consumption results are lower than those of state-ofart 3D DCT/IDCT implementations (tens of watts for software-based solutions [33] and several tens of megawatts for known custom hardware designs [34]). …”

Section: Power Consumption Resultsmentioning

confidence: 91%

“…Pure software implementations of 3D DCT on programmable cores have been proposed in [33]. By targeting general purpose multi-core processors, such as the Intel Core DUO architecture, a software optimized design of a 3D DCT and IDCT can be implemented in real time at 24 frames/s VGA format (640 9 480 pixels) on a Intel Core 2 6300@1.86 GHz.…”

Section: Paper Outlinementioning

confidence: 99%

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Real-time and low-power processing of 3D direct/inverse discrete cosine transform for low-complexity video codec

Saponara

2010

J Real-Time Image Proc

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The 3D discrete cosine transform and its inverse (3D DCT/IDCT) extend the spatial compression properties of conventional 2D DCT to the spatio-temporal coding of 2D videos. The 3D DCT/IDCT transform is particularly suited for embedded systems needing the low-complexity implementation of both video encoder and decoder, such as mobile terminals with video-communication capabilities. This paper addresses the problem of real-time and low-power 3D DCT/IDCT processing by presenting a context-aware fast transform algorithm and a family of VLSI architectures characterized by different levels of parallelism. Implemented in submicron CMOS technology, the proposed hardware macrocells support the real-time processing of main video formats (up to high definition ones with an input rate of tens of Mpixels/s) with different trade-offs between circuit complexity, power consumption and computational throughput. Voltage scaling and adaptive clock-gating strategies are applied to reduce the power consumption versus the state of the art

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Section: Power Consumption Resultsmentioning

confidence: 91%

Section: Paper Outlinementioning

confidence: 99%

Real-time and low-power processing of 3D direct/inverse discrete cosine transform for low-complexity video codec

Saponara

2010

J Real-Time Image Proc

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“…(1) Hardware platforms achieving real time for handheld/mobile devices at power costs lower than 1 Watt, but limited to a specific algorithm, for example, [22-25, 27-29, 32, 33]. (2) Software implementation on general purpose processors with clock frequencies in the GHz domain and with a single-core, for example, Atom in [26], or multicores, for example, Core2 in [26,34], depending on the computational load. The power consumption of such solutions is up to tens of Watts.…”

Section: Computing Architectures For Multimedia Processingmentioning

confidence: 99%

“…In [26], an Intel Core 2 6600@2.4 GHz implements the SIFT algorithm with a processing-rate of 16 Hz for VGA format. In [34], an Intel Core 2 6300@1.86 GHz achieves real-time processing of 3D DCT/IDCT codec for 24 Hz VGA format. Therefore, software implementations of multimedia processing tasks are possible although limited to suboptimal techniques.…”

Section: Computing Architectures For Multimedia Processingmentioning

confidence: 99%

Homogeneous and Heterogeneous MPSoC Architectures with Network‐On‐Chip Connectivity for Low‐Power and Real‐Time Multimedia Signal Processing

Saponara

Fanucci

2012

VLSI Design

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Two multiprocessor system-on-chip (MPSoC) architectures are proposed and compared in the paper with reference to audio and video processing applications. One architecture exploits a homogeneous topology; it consists of 8 identical tiles, each made of a 32-bit RISC core enhanced by a 64-bit DSP coprocessor with local memory. The other MPSoC architecture exploits a heterogeneous-tile topology with on-chip distributed memory resources; the tiles act as application specific processors supporting a different class of algorithms. In both architectures, the multiple tiles are interconnected by a network-on-chip (NoC) infrastructure, through network interfaces and routers, which allows parallel operations of the multiple tiles. The functional performances and the implementation complexity of the NoC-based MPSoC architectures are assessed by synthesis results in submicron CMOS technology. Among the large set of supported algorithms, two case studies are considered: the real-time implementation of an H.264/MPEG AVC video codec and of a low-distortion digital audio amplifier. The heterogeneous architecture ensures a higher power efficiency and a smaller area occupation and is more suited for low-power multimedia processing, such as in mobile devices. The homogeneous scheme allows for a higher flexibility and easier system scalability and is more suited for general-purpose DSP tasks in power-supplied devices.

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“…ME is also used as an integral part of a video encoder since many computing resources are needed. At the same time, ME contributes in particular to the difficulty of the encoder for its various block sizes and fractional pixel precision motion quest in the video encoding format H.264 [2]. Two main motion vector estimation techniques currently are available pel-recursive algorithm and the block matching algorithm.…”

Section: Introductionmentioning

confidence: 99%

Fuzzy based Search in Motion Estimation for Real Time Video Compression

Srivastava¹,

Kumar²

2021

IJACSA

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Video compression ratio, quality and efficiency are determined by the motion estimation algorithm. Motion estimation is used to perform inter frame prediction in video sequences. The individual frames are divided into blocks the motion estimation is computed by a video codec such as H.264. A video codec computes the displacement of block between the previous frame (reference frame) and the current frame, for each block in current frame the best motion vector is determined in the reference frame as a block belongs to a current frame. In this, research paper, a novel technique has been presented for motion vector calculation, using fuzzy Gaussian membership function. The motion estimation block uses fuzzy membership function to estimate the connectedness of different blocks of the current frame to that of the reference frame The fuzzy decision matching is done based on the matching criterion and the best matching block is selected. The motion vectors are thus calculated with respect to the reference frame. The fuzzification process produces optimally matched blocks, which are then utilized to calculate the motion vectors of the predicted frame. Using fuzzy based search the search area is automatically updated and adaptive search steps provides an optimized result of search. As in real time streaming no file is exchanged during the transmission user is not able to download the file the only way for smooth transmission is frame management fuzzy based search for the motion estimation provides a better compression for the predicted frames.

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Introduction to implementation of real time video compression method

Cited by 4 publications

References 4 publications

Real-time and low-power processing of 3D direct/inverse discrete cosine transform for low-complexity video codec

Real-time and low-power processing of 3D direct/inverse discrete cosine transform for low-complexity video codec

Homogeneous and Heterogeneous MPSoC Architectures with Network‐On‐Chip Connectivity for Low‐Power and Real‐Time Multimedia Signal Processing

Fuzzy based Search in Motion Estimation for Real Time Video Compression

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