Introduction of permissible bridges with application to logic optimization after technology mapping

Abstract

AbstTact -This paper introduces the concept of a permissible bridge and a permissible bridge pair. A bridge is a logic node with two inputs and one output. A bridge or a bridge pair are called permissible if they can be inserted into a Boolean network without changing its behavior at primary outputs. There are a total of 255 types of bridges that can be considered between any pair of wires in the network. We discuss a subset of such bridges and present three theorems related to permissible bridges for pairwise detectability, distinguishability and conditional equivalence. Experimental results show that relatively many bridges are permissible in each circuit. In this paper, we exploit the conditional equivalence of wire pairs and show that even after technology mapping, we can significantly reduce the active area as well as the wiring of many designs.

Logic optimization and equivalence checking by implication analysis

“…The approach to be presented in this paper can be seen as a generalization of the technique in [16] applied to combinational circuits. The advantage of operating directly on the gate netlist has also been recognized by Rohfleisch and Brglez [32] who presented a technique based on permissible bridges which can effectively optimize a circuit after technology mapping.…”

“…Even with much recent progress, e.g., [3], [8], [10], [14], [16], [18], [19], [25]- [27], [31], [32], [34], and [38], the size and complexity of today's integrated circuits leave multilevel logic optimization a major challenge in the field of computeraided circuit design. In particular, high-memory requirements represent the dominating limitation for many methods.…”

“…The methods of [16] and [32] have been shown to be very useful for postprocessing networks that were preoptimized by traditional techniques. On the other hand, they only consider a restricted set of possible network manipulations and, therefore, do not provide the same reasoning power and flexibility as traditional technology-independent synthesis methods.…”

Functional extension of structural logic optimization techniques

“…During the last years, new logic optimization methods have been proposed that are based on ATPG concepts and techniques [1][2][3][4][5][6][7][8]. Contrast to the more traditional methods based on techniques to identify common sub expressions, ATPG-based methods exploit the concept of redundancy in a direct manner and perform logic optimization by an iterative addition and removal of redundancies.…”

“…These methods have demonstrated to produce excellent results, being the major advantages the low memory usage and the short run times. On the other hand, they are suitable for post-mapping and postlayout optimization, as they can work satisfactorily under technological constraints [3] [7].…”