Introducing NoC 2 : Interconnecting NoC-based Systems through Ethernet

Hassan, Ahmed S.; Morgan, Ahmed A.; El-Kharashi, M. Watheq

doi:10.1016/j.procs.2017.06.125

Cited by 2 publications

(2 citation statements)

References 12 publications

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“…This paper is a significant extension and update of a paper that appeared in the proceedings of the 4th Workshop on Design and Performance of Networks on Chip (DPNoC 2017) in conjunction with the The 12th International Conference on Future Networks and Communications (FNC 2017) [33]. All trademarks ™ and registered trademarks ® mentioned, cited, or referenced in this document remain the property of their respective owners.…”

Section: Acknowledgmentmentioning

confidence: 92%

Networks-on-Chip Interfacing: NoC-based Systems Networking and Inter-NoC Communication

Hassan¹

2017

IJCDS

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Many-and multi-core Networks-on-Chip (NoC) systems have a large spectrum of applications, and one of these applications is High Performance Computing (HPC). In HPC application, system scalability is one of the important features of a given HPC platform. Two of the factors governing scalability are the interfacing link speed and the ease of deploying additional processing nodes. For NoC-based systems, scalability has two meanings; intra-NoC scalability, which includes partitioning and clustering Processing Elements (PEs) to achieve better performance, and inter-NoC scalability, which includes interfacing with other NoC-based systems via inter-NoC links and creating a newtrok of multiple NoC-based systems. In this paper, we investigate the case of inter-NoC communication between a network of NoC-based systems. By using our simulator, we found out that treating a network of NoC-based systems as a generic case of interfacing yields non-optimal performance. To target the inter-NoC communication performance, we introduce NoC 2 , an NoC-based system with an Ethernet communication manager that provides better management for inter-NoC traffic. Current implementations of inter-NoC traffic management handle inter-NoC traffic using software running on top of a dedicated PE, whereas NoC 2 is designed so that the software running on cores within the NoC is completely abstracted from inter-NoC traffic management. Experiments show that this kind of abstraction has better inter-NoC communication performance over generic NoC interfaced via Ethernet. Results suggest that NoC 2 would perform better when it comes to scaling NoC-based systems by interfacing more NoC-based hardware.

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Section: Acknowledgmentmentioning

confidence: 92%

Networks-on-Chip Interfacing: NoC-based Systems Networking and Inter-NoC Communication

Hassan¹

2017

IJCDS

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“…In this paper, we will show that the performance of these techniques is not optimal. Moreover, supported by our initial work in [6], we present a more efficient interfacing approach. Our approach is meant to work in conjunction with previous CNoC architecture customization techniques to properly handle their inter-cluster traffic and further enhance their performance.…”

Section: Introductionmentioning

confidence: 99%

NoC²: An Efficient Interfacing Approach for Heavily-Communicating NoC-Based Systems

et al. 2020

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Current research in interfacing clusters within Hierarchical Networks-on-Chip (HNoC) as well as interfacing NoC-based systems adopts a centralized approach. In this approach, a specific Processing Element (PE) acts as a gateway between interfacing peripherals and the rest of NoC elements. This paper evaluates this approach and show that it is not optimal for handling the inter-NoC communication. Routing inter-NoC traffic through a system to its gateway PE deteriorates the network performance. Results show that both the throughput and latency of the centralized approach degrade with the increase in the inter-NoC traffic bandwidth. To alleviate this, we propose a novel distributed approach, which separates the inter-NoC traffic from the intra-NoC one. Our approach relies on distributed buffers to allow PEs to efficiently communicate with the interfacing peripheral. We evaluate our approach against other interfacing ones using synthetic traffic as well as real benchmark applications. Our evaluation covers the whole system performance as well as its inter-and intra-NoC parts. Results prove that the proposed approach outperforms previous interfacing ones in terms of throughput and latency. The proposed approach significantly enhances the inter-NoC performance without any deterioration in the intra-NoC one. Considering the inter-NoC performance, we achieve a throughput that is close to the maximum possibly attainable one. Other approaches show major performance degradation, reaching as low as 10% of this maximum attainable throughput. INDEX TERMS Hierarchical Networks-on-Chip (HNoC), Inter-NoC communication, Intra-NoC communication, NoC benchmarks, NoC Ethernet, NoC high-speed interfacing, NoC Time Division Multiple Access (TDMA), NoC traffic.

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Introducing NoC 2 : Interconnecting NoC-based Systems through Ethernet

Cited by 2 publications

References 12 publications

Networks-on-Chip Interfacing: NoC-based Systems Networking and Inter-NoC Communication

Networks-on-Chip Interfacing: NoC-based Systems Networking and Inter-NoC Communication

NoC²: An Efficient Interfacing Approach for Heavily-Communicating NoC-Based Systems

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Introducing NoC 2 : Interconnecting NoC-based Systems through Ethernet

Cited by 2 publications

References 12 publications

Networks-on-Chip Interfacing: NoC-based Systems Networking and Inter-NoC Communication

Networks-on-Chip Interfacing: NoC-based Systems Networking and Inter-NoC Communication

NoC2: An Efficient Interfacing Approach for Heavily-Communicating NoC-Based Systems

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NoC²: An Efficient Interfacing Approach for Heavily-Communicating NoC-Based Systems