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One of the challenging problems in networks-on-chip (NoC) design is optimising the architectural structure of the on-chip network in order to maximise the network performance while minimising the corresponding costs. In this study, a methodology for multi-objective optimisation of NoC standard architectures using Genetic Algorithms is presented. The methodology considers two cost metrics, power and area, and two performance metrics, delay and reliability. Our methodology combines the best selection of NoC standard topology, the optimum mapping of application cores onto that topology, and the best routing of application traffic traces over the generated network. The methodology is evaluated by applying it to different NoC benchmark applications as case studies. Results show that the architectures generated by our methodology outperform those of other standard architecture customisation techniques with respect to four metrics: power, area, delay and reliability, and their combination.

Mobile health monitors allow patients to leave the hospital and engage in normal activity, uploading physiological data only periodically. Most existing systems use fixed gateways to upload data to the server. The Wireless Distributed Data Acquisition System presented in this paper is developed for prolonged, synchronized, healthhtress monitoring of a selected group of subjectdpatients. The system is based on mobile client devices, and mobile gateways. We use personal digital assistant (PDA) as a mobile gateway to collect data from individual monitors, and synchronize collected records with existing records on the telemedical server. Each client device uses flash memory as a temporary storage until the reliable connection with a mobile gateway is established. Individual intelligent sensors are based on a very low-power microcontroller TI MSP430F149, and use standard 900 MHz wireless link, and flash memory. This system is used to evaluate the effects of stressful military training. We have found that patterns of heart rate variability correlate with stress tolerance.

Networks-on-Chip (NoC) architecture design faces a trade-off between different conflicting metrics. In this paper, we target one aspect of this trade-off: area versus average delay. The NoC architecture generation is formulated as a twoobjective optimization problem and a Genetic Algorithm (GA)-based technique is used to solve it. According to the application requirements and the design constraints, the optimization process could be controlled by the designer by specifying weight factors for area and delay. As a proof of concept, our technique is applied to three real applications with different number of cores. Results show that the proposed solution is a promising way to achieve the best architecture with respect to both area and delay.

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Network reliability is a key design issue that impacts the performance of all Networks-on-Chip-based systems. In this paper, we develop two reliability models for on-chip interconnection networks using both deterministic and probabilistic measures. Graph-theoretic concepts are adopted with modifications to obtain application-specific reliability models for nine regular network topologies. Using these models, a new methodology is proposed to improve the network reliability of any target application using a topology-based design approach. To validate the effectiveness of the proposed methodology, a case study was performed using an MPEG4 video application. The results were promising and proved that the proposed methodology helps designers better evaluate the impact of their network architecture on the system reliability and assists them in choosing the most appropriate architecture for a target application at early design phases.

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