Interpolated timing recovery for hard disk drive read channels

Spurbeck, M.S.; Behrens, R.T.

doi:10.1109/icc.1997.595061

Cited by 27 publications

(5 citation statements)

References 6 publications

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“…This approach is commonly used in symbol-rate sampled receivers as in the case of direct-detection-based receivers. Another option for the timing recovery is to employ a time domain fractional delay filter to resample the signal and align samples and symbols [9]. In this case, the clock of the ADC is free running.…”

Section: A Inter-data Center (Coherent) Dspmentioning

confidence: 99%

Recent Advances in Low-Power Digital Signal Processing Technologies for Data Center Applications

Nagarajan,

Martino,

Morero

et al. 2024

J. Lightwave Technol.

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The explosive growth of artificial intelligence (AI) has resulted in an exponential growth of demand for bandwidth in datacenters. We have reached a point where this growth becomes limited by the power that can be physically supplied to the datacenters, imposing an important constraint on the hardware that can be deployed. Pluggable optical modules, enabled by low power DSPs, are used extensively for high-speed interconnects in datacenters. However, the explosive growth of bandwidth, constrained by a fixed power envelope, is a continuous challenge. Although other approaches, such as copackage optics and linear drive optics, are starting to appear, this paper focuses on recent innovations and tradeoffs that has allowed DSPs to keep pace with the bandwidth growth in intradatacenter and inter-datacenter interconnect applications.

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Section: A Inter-data Center (Coherent) Dspmentioning

confidence: 99%

Recent Advances in Low-Power Digital Signal Processing Technologies for Data Center Applications

Nagarajan,

Martino,

Morero

et al. 2024

J. Lightwave Technol.

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“…The SRC forms part of a timing-recovery loop which is not depicted explicitly (see References [6,Chapter 9,7] for an introduction to SRC-based timing recovery). Rather than placing the equalizer before the SRC, it would be possible to reverse their order.…”

Section: Introductionmentioning

confidence: 99%

Asynchronous zero-forcing adaptive equalization

Bergmans

Pozidis

Lin

2005

Eur. Trans. Telecomm.

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SUMMARYDigital data receivers often operate at a fixed sampling rate 1=T s that is asynchronous to the baud rate 1=T. A digital equalizer that processes the incoming signal will also be asynchronous, and its adaptation is commonly based on extensions of the LMS algorithm. In this paper, we develop and analyze a much simpler approach that is based on zero-forcing adaptation techniques. Numerical results for an idealized optical recording channel serve to illustrate the merits of the approach. LMS-like performance is found to be within reach at a fraction of the cost of LMS.

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“…1(b)) samples the received signal without phase locking to the signal. The CDR then interpolates between the blind samples to obtain a new set of samples in order to recover phase and data [5], [6]. The interpolator, however, is relatively complex and since it remains in the CDR loop, it contributes to the loop latency.…”

mentioning

confidence: 99%

“…2(c). To recover clock and data, the CDR interpolates between the blind samples, , a new set of two samples per UI-the phase-locked set [5], [6]. In the phase-locked set, one sample is close to UI center and the other sample is close to UI edge.…”

mentioning

confidence: 99%

A 5-Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS

Tyshchenko

Sheikholeslami

Tamura

et al. 2010

IEEE J. Solid-State Circuits

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Abstract-This paper presents an ADC-based CDR that blindly samples the received signal at twice the data rate and uses these samples to directly estimate the locations of zero crossings for the purpose of clock and data recovery. We successfully confirmed the operation of the proposed CDR architecture at 5 Gb/s. The receiver is implemented in 65 nm CMOS, occupies 0.51 mm 2 , and consumes 178.4 mW at 5 Gb/s.Index Terms-Clock and data recovery, CDR, ADC-based CDR, feed-forward CDR, blind-sampling CDR, all-digital CDR.

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Interpolated timing recovery for hard disk drive read channels

Cited by 27 publications

References 6 publications

Recent Advances in Low-Power Digital Signal Processing Technologies for Data Center Applications

Recent Advances in Low-Power Digital Signal Processing Technologies for Data Center Applications

Asynchronous zero-forcing adaptive equalization

A 5-Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS

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