2023
DOI: 10.1021/acsaelm.3c00256
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Interplay Between Strain and Thickness on the Effective Carrier Lifetime of Buffer-Mediated Epitaxial Germanium Probed by the Photoconductance Decay Technique

Abstract: We report contactless effective minority carrier lifetime of epitaxially grown unstrained and in-plane <110> biaxially tensile-strained (001) germanium (ε-Ge) epilayers measured using microwave-reflectance photoconductance decay measurements. Strained Ge epilayers were grown using In x Ga 1−x As linearly graded buffers on (001) GaAs substrates. Using homogeneous excitation of unstrained Ge epilayers, thickness-dependent separation of minority carrier lifetime components under low injection conditions yielded a… Show more

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Cited by 2 publications
(9 citation statements)
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“…For this work, we used the μ-PCD technique to characterize the effect of the underlying buffer and top overgrowth on the effective carrier lifetime in the ε-Ge epilayers. Details of the measurement technique have been reported in our previous work . Under low-injection conditions, it can be shown that the reciprocal of effective carrier lifetime, τ eff , is expressed as the cumulative response from two reciprocal components, τ surface and τ bulk , as follows: , 1 τ eff = 1 τ surface + 1 τ bulk where τ surface and τ bulk are effective lifetime components from the surface and bulk, respectively.…”
Section: Resultsmentioning
confidence: 99%
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“…For this work, we used the μ-PCD technique to characterize the effect of the underlying buffer and top overgrowth on the effective carrier lifetime in the ε-Ge epilayers. Details of the measurement technique have been reported in our previous work . Under low-injection conditions, it can be shown that the reciprocal of effective carrier lifetime, τ eff , is expressed as the cumulative response from two reciprocal components, τ surface and τ bulk , as follows: , 1 τ eff = 1 τ surface + 1 τ bulk where τ surface and τ bulk are effective lifetime components from the surface and bulk, respectively.…”
Section: Resultsmentioning
confidence: 99%
“…The Ge epilayers in heterostructures A and B in this work are grown well within the critical layer thickness, adhering to the strain balance model by People and Bean, and hence, the Ge epilayers should be fully strained. This is indeed observed in our previous work where high-magnification transmission electron micrographs obtained from the constant composition InGaAs virtual substrate, the ε-Ge epilayer, and the ε-Ge/InGaAs heterointerface show a high degree of coherence and absence of misfit dislocations, alluding to the pseudomorphic epitaxy of Ge. The exact cause for this observed disparity between XRD- and Raman-estimated strain levels, especially on InAlAs buffer, currently eludes the authors and needs additional research.…”
Section: Resultsmentioning
confidence: 99%
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“…The lower Al 2 O 3 thickness was selected for lower EOT. As high-quality GeO 2 ,,, IPL layer is necessary for passivating surface defects of Ge, thermal oxidation of 0.2% ε-Ge and 1.2% ε-Ge stack was carried out at 550 °C (which is the highest oxidation temperature one can select in order to prevent the strain relaxation in this work) for different oxidation duration. Figure shows the C – V characteristics of the Ge MOS-Cs of (a) 0.2% ε-Ge, where GeO 2 oxidation was performed only for 0.5 min, and (b–d) 1.2% ε-Ge where oxidation duration was varied from 0.5 to 2.5 min, respectively.…”
Section: Resultsmentioning
confidence: 99%
“…Group IV based materials, germanium (Ge), silicon–germanium (SiGe), and germanium–tin (GeSn), are under consideration for nanoelectronics and photonics. Due to their high carrier mobilities, supplementing these materials along with tunable compositional In x Ga 1– x As (0.1 ≤ x ≤ 0.4) as channel materials will boost the on-current and ultimately device/circuit performance in an alternate channel CMOS, , tensile-strained Ge/In x Ga 1– x As based tunnel transistors, , energy-efficient SRAM cell architecture for ultralow voltage applications, and photonic devices. ,,, For high-performance ultralow voltage CMOS logic, RF circuits, and mixed signal low-noise amplifier circuits, it is widely accepted that InGaAs and Ge will serve as n -channel and p -channel transistor materials, respectively. ,− However, implementing these two different materials (i.e., Ge and InGaAs) on a Si wafer requires defect-controlled buffer engineering for the monolithic heterogeneous integration process rather than direct growth of Ge or SiGe on Si. Furthermore, Ge is an excellent choice for CMOS logic due to its 2.8× and 4.2× higher electron and hole mobilities, respectively, compared to Si.…”
Section: Introductionmentioning
confidence: 99%