Intermediate Representations for Design Automation of Multiprocessor DSP Systems

Abstract

Abstract. Self-timed scheduling is an attractive implementation style for multiprocessor DSP systems due to its ability to exploit predictability in application behavior, its avoidance of over-constrained synchronization, and its simplified clocking requirements. However, analysis and optimization of selftimed systems under real-time constraints is challenging due to the complex, irregular dynamics of selftimed operation. In this paper, we review a number of high-level intermediate representations for compiling dataflow programs onto self-timed DSP platforms, including representations for modeling the placement of interprocessor communication (IPC) operations; separating synchronization from data transfer during IPC; modeling and optimizing linear orderings of communication operations; performing accurate design space exploration under communication resource contention; and exploring alternative processor assignments during the synthesis process. We review the structure of these representations, and discuss efficient techniques that operate on them to streamline scheduling, communication synthesis, and power management of multiprocessor DSP implementations.

Modeling pipelined application with Synchronous Data Flow graphs

“…The enriched graph describes only periodic staticorder schedule, i.e., the scheduling is specified only for each single processor and no information about inter processors synchronization is added. Both scheduling and mapping are instead described in the Interprocessor Communication SDF Graphs (IPC graphs) proposed by Bambha et al [8]. The graphs are built starting from a design solution and describe the sequence of actor activations for each processing element and the communications among them.…”

“…Since the ordering of the actor activations which compose a PSOS is absolute, this can be described by simply specifying the order between each pair of activations: all the other relative orderings will be implied by these. DSM forces the actor of choice of a decision state to be executed before all the other active actors, but to guarantee the satisfaction of the required schedule it is sufficient to impose that in each decision state the actor of choice is executed before the actor which follows it in the schedule (lines [8][9][10][11][12][13][14][15][16][17][18][19]). This optimization, like the ones proposed in [2], aims at reducing the size of the produced graph, but since they are not equivalent, they have all to be applied in order to produce the smallest graph.…”

Analyzing composability of applications on MPSoC platforms

“…In [1], the authors propose to analyze performance of a single application modeled as an SDF graph (SDFG) mapped on a multi-processor system by decomposing it into a homogeneous SDFG (HSDFG) [21], and modeling dependencies of resources by adding extra edges on the vertices. Vertices model actors in the application.…”

“…This is achieved by appending a small message at the end of the output actor of the application graph 1 . This allows the RM to monitor the progress of each application at little cost.…”

Modeling static-order schedules in synchronous dataflow graphs

“…Such a schedule is called a periodic static-order schedule (PSOS). PSOSs specify the order of actor firing which separates them There is only one technique [11] known to model PSOSs in an SDFG. This technique requires a conversion of an SDFG to a so-called homogeneous SDFG (HSDFG) in which all rates are equal to one [2].…”