Interleaving Impact on AC Passive Components of Paralleled Three-Phase Voltage-Source Converters

Zhang, Di; Wang, F.; Burgos, Rolando; Lai, Rongjie; Boroyevich, Dushan

doi:10.1109/08ias.2008.292

Cited by 44 publications

(29 citation statements)

References 10 publications

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“…Using the double integral Fourier analysis method [17], the output ac harmonic currents cancellation effect of interleaving for a system of N parallel three-phase VSCs has theoretically been confirmed [13]. The impact of the non-conventional interleaving is also discussed in [15,18,19] and used in [16]. In summary, the previous work discussed above mainly focuses on symmetric interleaving and the impact of interleaving on system harmonic voltages and currents.…”

Section: Principle Of Asymmetric Interleavingmentioning

confidence: 99%

Asymmetric interleaving in low-voltage CMOS power management with multiple supply rails

Schuck

Pilawa-Podgurski

2014

2014 IEEE Energy Conversion Congress and Exposition (ECCE)

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Recent years have seen the proliferation of electronic devices that require multi-phase power converters to provide heterogeneous power rails to different systems. Typical systems will utilize symmetric interleaving as a method of reducing the input current ripple for the power converter. Asymmetric interleaving is a method of control that allows for a further reduction, and in some cases complete cancellation, of this input current ripple. This work looks at some of the challenges for a practical implementation using digital control, and provides results to quantify this improvement. This work demonstrates a control algorithm implementation capable of achieving nearly 3x reduction in the input current ripple via the asymmetric interleaving method.

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Section: Principle Of Asymmetric Interleavingmentioning

confidence: 99%

Asymmetric interleaving in low-voltage CMOS power management with multiple supply rails

Schuck

Pilawa-Podgurski

2014

2014 IEEE Energy Conversion Congress and Exposition (ECCE)

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“…Increasing impedance and reduce CMV methods [7][8][9][10]: In [7], a common mode choking coil is used to increase the impedance of ZSCC, and DPWM method is utilized to reduce the CMV. In [8][9][10], interleaving inductance and DPWM methods are used. However, there are open loop control methods.…”

Section: Introductionmentioning

confidence: 99%

Elimination of zero sequence circulating current between parallel operating three-level inverters

Wang

Dong

et al. 2016

IECON 2016 - 42nd Annual Conference of the IEEE Industrial Electronics Society

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Abstract-In order to suppress the zero sequence circulating currents (ZSCCs) between parallel operating three level voltage source inverters with common AC and DC buses, a common mode voltage reduction PWM (CMVR-PWM) technique and neural point potentials (NPPs) control based method is proposed in this paper. An equivalent model of ZSCC is developed, and two excitation sources of ZSCC, differences of common mode voltages (CMVs) and NPPs between paralleled inverters, are analyzed. A CMVR-PWM method is investigated to reduce the CMV, and a simple electric circuit is adopted to control the NPPs. With this two strategies, ZSCCs between parallel inverters can be eliminated effectively. This strategy has the advantage of without carrier synchronization and can be utilized to parallel operating inverters with different types of filter. Simulation result validate the proposed ZSCC elimination schemes.

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“…Therefore, there exists a potential difference that further increases the circulating current [16]. This is a high frequency circulating current with harmonic components concentrated around the odd multiples of the switching frequency [12]. This unwanted current increases stress on the semiconductor switches and causes additional losses.…”

Section: Introductionmentioning

confidence: 99%

Modified Discontinuous PWM for Size Reduction of the Circulating Current Filter in Parallel Interleaved Converters

Gohil

Maheshwari

Bede

et al. 2015

IEEE Trans. Power Electron.

104

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Suggested citation format:Gohil, G.; Maheshwari, R.; Bede, L.; Kerekes, T.; Teodorescu, R.; Liserre, M.; Blaabjerg, F., "Modified Discontinuous PWM for Size Reduction of the Circulating Current Filter in Parallel Interleaved Converters," IEEE Transactions on Power Electronics , vol.30, no.7, pp.3457,3470, July 2015. General rightsCopyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognize and abide by the legal requirements associated with these rights. Users may download and print one copy of any publication from the public portal for the purpose of private study or research.  You may not further distribute the material or use it for any profit-making activity or commercial gain.  You may freely distribute the URL identifying the publication in the public portal. Take down policyIf you believe that this document breaches copyright please contact us at vbn@aub.aau.dk providing details, and we will remove access to the work immediately and investigate your claim. Abstract-Parallel Voltage Source Converters (VSCs) require an inductive filter to suppress the circulating current. The size of this filter can be minimized by reducing either the maximum value of the flux linkage or the core losses. This paper presents a modified Discontinuous Pulsewidth Modulation (DPWM) scheme to reduce the maximum value of the flux linkage and the core losses in the circulating current filter. In the proposed PWM scheme, the dwell time of an active vector is divided within a half-carrier cycle to ensure simultaneous occurrence of the same zero vectors in both VSCs. A function to decide the ratio of the dwell time of the divided active vector is also presented. The effect of the proposed PWM scheme on the maximum value of the flux linkage and the core losses is analyzed and compared with that of the space vector modulation and 60• clamped DPWM schemes. The analytical expressions for the maximum value of the flux linkage are derived for each of these PWM schemes. In addition, the effect of the proposed PWM scheme on the line current ripple and the switching losses is also analyzed and compared. To verify the analysis, experimental results are presented, which prove the effectiveness of the proposed PWM scheme.

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Interleaving Impact on AC Passive Components of Paralleled Three-Phase Voltage-Source Converters

Cited by 44 publications

References 10 publications

Asymmetric interleaving in low-voltage CMOS power management with multiple supply rails

Asymmetric interleaving in low-voltage CMOS power management with multiple supply rails

Elimination of zero sequence circulating current between parallel operating three-level inverters

Modified Discontinuous PWM for Size Reduction of the Circulating Current Filter in Parallel Interleaved Converters

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