Asymmetric interleaving in low-voltage CMOS power management with multiple supply rails

Ho, Aaron D.; Schuck, Marcel; Pilawa-Podgurski, Robert C. N.

doi:10.1109/ecce.2014.6953416

Cited by 5 publications

(4 citation statements)

References 35 publications

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“…However, computational requirements are increased. Reference [33] contains an analysis of the trade-off between lookup table size and computing time for a related application. The corresponding control architecture for adjusting the phase-shift of all three converters is shown in Fig.…”

Section: Resultsmentioning

confidence: 99%

“…This will facilitate ripple minimization in DMPPT applications such as described in [20]- [28]. Our previous work in this area can be found in [30]- [33]. A key contribution of our proposed analysis technique is that it is based on a more universally applicable frequencydomain description of the converter current waveforms, as opposed to a time-domain description as outlined in [34], [35].…”

Section: Mathematical Description Of the Problemmentioning

confidence: 99%

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Ripple Minimization Through Harmonic Elimination in Asymmetric Interleaved Multiphase DC–DC Converters

Schuck

Pilawa-Podgurski

2015

IEEE Trans. Power Electron.

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Symmetric multiphase dc-dc converters are widely used in power electronics, as they enable the processing of high power through splitting the overall load-current into multiple phases. Distributing the processed power symmetrically between the phases and performing ripple minimization through interleaving is well understood. However, in recent applications such as maximum power point (MPP) tracking for solar photovoltaic (PV), converters are forced to operate under asymmetric conditions, due to differences in the sources or loads of each converter. This work presents a control technique, based on harmonic elimination, that allows for ripple minimization under asymmetric conditions. The mathematical derivations are outlined and simulations are used to evaluate the performance of the proposed technique. Measurements taken from an experimental prototype, consisting of three dc-dc buck converters, demonstrate significant improvements in ripple reduction over conventional interleaving techniques. When the multi-phase converter is operated at the optimum asymmetric phase-shift found through the techniques presented here, a more than 3x reduction in net current ripple is observed under realistic operating conditions. Additionally, the undesirable first harmonic ripple component is reduced by 14.8 dB with the proposed technique.

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Section: Resultsmentioning

confidence: 99%

Section: Mathematical Description Of the Problemmentioning

confidence: 99%

Ripple Minimization Through Harmonic Elimination in Asymmetric Interleaved Multiphase DC–DC Converters

Schuck

Pilawa-Podgurski

2015

IEEE Trans. Power Electron.

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“…The boxed area of Figure 3c highlights the system components that are considered in this work, which constitute four series-connected cells and one MPPT. The parallel output connection of the individual MPPT converters can be further utilized for interleaved operation and ripple cancellation [17], [18], enabling smaller individual output capacitance for each converter. Moreover, since our proposed MPPT converter provides maximization of its input power, there is no inadvertent coupling between parallel MPPT converters.…”

Section: A Conventional Mppt Architecturementioning

confidence: 99%

“…The P&O technique is well-suited for digital implementation, which we have chosen for our 0.35 µm CMOS design. Digital control was chosen for its flexibility in operating conditions, as we explore switching frequencies over 500 kHz-1.5 MHz, as well as the future possibility of synchronizing the operation of several MPPT converters to achieve ripple reduction through interleaved operation [17], [18]. Moreover, the operating conditions in our intended application are expected to change very slowly with time, enabling very low MPPT update frequencies.…”

Section: System Overviewmentioning

confidence: 99%

Integrated CMOS Energy Harvesting Converter With Digital Maximum Power Point Tracking for a Portable Thermophotovoltaic Power Generator

Pilawa-Podgurski

Čelanović

et al. 2015

IEEE J. Emerg. Sel. Topics Power Electron.

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Abstract-This paper presents an integrated maximum power point tracking system for use with a thermophotovoltaic (TPV) portable power generator. The design, implemented in 0.35 µm CMOS technology, consists of a low-power control stage and a dc-dc boost power stage with soft-switching capability. With a nominal input voltage of 1 V, and an output voltage of 4 V, we demonstrate a peak conversion efficiency under nominal conditions of over 94% (overall peak efficiency over 95%), at a power level of 300 mW. The control stage uses lossless current sensing together with a custom low-power time-based ADC to minimize control losses. The converter employs a fully integrated digital implementation of a peak power tracking algorithm, and achieves a measured tracking efficiency above 98%. A detailed study of achievable efficiency versus inductor size is also presented, with calculated and measured results.

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ESD Improvements on Power N-Channel LDMOS Devices by the Composite Structure of Super Junctions Integrated With SCRs in the Drain Side

Chen

Huang

et al. 2020

IEEE J. Electron Devices Soc.

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This paper studies a composite power n-channel lateral-diffused MOSFET device with a super junction (SJ) and parasitic silicon-controlled rectifier structure (nLDMOS-SJ-SCR) in the drain side, which can be used for electrostatic discharge (ESD) and latch-up (LU) reliability enhancements of 60-V power electronics. For ESD and LU protection considerations, the drain side with an SJ structure integrated with p-n-p-and n-p-n-arranged types of nLDMOS-SCR transistors is demonstrated. According to the experimental data, the layout of the SJ structure in the drain side has positive effects on ESD and LU capabilities. The layout type of nLDMOS-SJ with a pillar width W= 9 μm has the highest secondary breakdown current (It2) values; the ESD (LU) improvement was 46.3% (13.3%) compared with the nLDMOS reference sample. Meanwhile, an nLDMOS-SJ with a pillar width W= 27 μm has the highest figure of merit (FOM) value. By contrast, an embedded p-n-p-(n-p-n-)arranged type SCR structure was added into the drain side once again. Initially, it has a positive (negative) effect on the ESD reliability. Furthermore, the ESD (figure of merit; FOM) improvement was 37.9% (13.72%) of the corresponding nLDMOS-SJ device for nLDMOS-SJ-SCR (p-n-p) with W= 27 μm. Overall, an nLDMOS-SJ device integrated with the p-n-p-arranged-type SCR in the drain side is a favorable choice for ESD and LU improvements.

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Asymmetric interleaving in low-voltage CMOS power management with multiple supply rails

Cited by 5 publications

References 35 publications

Ripple Minimization Through Harmonic Elimination in Asymmetric Interleaved Multiphase DC–DC Converters

Ripple Minimization Through Harmonic Elimination in Asymmetric Interleaved Multiphase DC–DC Converters

Integrated CMOS Energy Harvesting Converter With Digital Maximum Power Point Tracking for a Portable Thermophotovoltaic Power Generator

ESD Improvements on Power N-Channel LDMOS Devices by the Composite Structure of Super Junctions Integrated With SCRs in the Drain Side

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