Interlayer electron modulation in van der Waals heterostructures assembled by stacking monolayer MoS<sub>2</sub> onto monolayer graphene with different electron transfer ability

Wang, Zhenping; Cao, Qing; Sotthewes, Kai; Hu, Yingbin; Shin, Hyeon Suk; Eigler, Siegfried

doi:10.1039/d1nr03708k

Cited by 8 publications

(18 citation statements)

References 46 publications

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“…19 The h-BN and PdSe 2 flakes were exfoliated from respective bulk crystals and then stacked onto the bottom metal electrode (5 nm Ti/20 nm Au) using a dry transfer technique. 20,21 The h-BN flakes with a similar thickness of about 20 nm, which serve as the dielectric layers, provide ultraclean and atomically flat surfaces to minimize impurities and disorder coming from the underlying metal surfaces. Two categories of PdSe 2 were chosen: group A: few-layer PdSe 2 flakes with a thickness of ∼4 nm, and group B: multilayer PdSe 2 with a thickness of ∼10 nm.…”

Section: ■ Results and Discussionmentioning

confidence: 99%

“…The vertical two-terminal MISM capacitor structure can be used to investigate the intrinsic trap behaviors between h-BN/PdSe 2 interfaces due to its advantage of eliminating the influence of large parasitic capacitance commonly observed from the C – V characteristics of lateral FET devices . The h-BN and PdSe 2 flakes were exfoliated from respective bulk crystals and then stacked onto the bottom metal electrode (5 nm Ti/20 nm Au) using a dry transfer technique. , The h-BN flakes with a similar thickness of about 20 nm, which serve as the dielectric layers, provide ultraclean and atomically flat surfaces to minimize impurities and disorder coming from the underlying metal surfaces. Two categories of PdSe 2 were chosen: group A: few-layer PdSe 2 flakes with a thickness of ∼4 nm, and group B: multilayer PdSe 2 with a thickness of ∼10 nm.…”

Section: Resultsmentioning

confidence: 99%

“…Vertical h-BN/PdSe 2 heterostructures were stacked by the PC transfer method onto the Si/SiO 2 (285 nm) substrates. The details of transfer and stacking processes were introduced in our previous research. , The electrodes were fabricated by standard EBL and EBD processes. Then, vacuum annealing was performed for 1 h at 90 °C in a rapid thermal annealing system (Korea Vacuum Tech., KVRTA-3004) before transport measurements.…”

Section: Methodsmentioning

confidence: 99%

“…After that, vertical h-BN/PdSe 2 heterostructures were stacked onto the prepatterned bottom electrodes (5 nm Ti/20 nm Au) by the dry transfer technique, with polycarbonate (PC) as a carrier. The details of transfer and stacking processes were introduced in our previous research. , To avoid environmental contamination and the formation of bubbles, the transfer processes were performed in a glovebox with moisture and oxygen concentrations lower than 1 ppm. Then, the top electrodes (5 nm Ti/70 nm Au) were deposited to cover the top surface of PdSe 2 flakes.…”

Section: Methodsmentioning

confidence: 99%

“…The details of transfer and stacking processes were introduced in our previous research. 20,21 To avoid environmental contamination and the formation of bubbles, the transfer processes were performed in a glovebox with moisture and oxygen concentrations lower than 1 ppm. Then, the top electrodes (5 nm Ti/70 nm Au) were deposited to cover the top surface of PdSe 2 flakes.…”

Section: ■ Experimental Sectionmentioning

confidence: 99%

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Probing Intrinsic Defect-Induced Trap States and Hopping Transport in Two-Dimensional PdSe₂ Semiconductor Devices

Wang

Ali

Choi

et al. 2022

ACS Appl. Mater. Interfaces

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Palladium diselenide (PdSe 2 ), as an emerging twodimensional (2D) layered material, is gaining growing attention in nanoelectronics and optoelectronics due to its thickness-dependent band gap, high carrier mobility, and good air stability. However, its asymmetric pentagon structure is inclined to breed defects. Herein, the intrinsic Se vacancy-induced trap states and their influence on the hopping transport in PdSe 2 are systematically investigated. We provide direct evidence that Se vacancies exist in the fresh PdSe 2 samples, which results in the localized trapping states inside the band gap. For the few-layer PdSe 2 , at 77 K, the trap density (D it ) near the midgap is about 2.2 × 10 13 cm −2 eV −1 , whereas at 295 K, the D it value increases to ∼7.1 × 10 13 cm −2 eV −1 . By comparison, the multilayer PdSe 2 shows nonobvious temperature-dependent trap behaviors with almost unchanged D it values of ∼8.1 × 10 12 cm −2 eV −1 at midgap in the temperature range between 77 and 295 K. Thus, trap states in the few-layer PdSe 2 are more vulnerable to temperature effect. Transport measurements demonstrated that both few-layer and multilayer PdSe 2 field-effect transistor (FET) devices show n-type dominant ambipolar behaviors. The electron mobility in the multilayer PdSe 2 FET is nearly 15-fold higher than that in the few-layer PdSe 2 FET at 315 K, probably owing to the decreased effective mass and suppression of charge impurity scattering in the thicker channel material. However, both FET devices exhibit variable-range hopping over a temperature range from 77 to 240 K and thermally activated hopping at temperatures above 240 K. The hopping transport mechanism is strongly associated with the Se vacancy-induced localized states with poor screening and strong potential fluctuations. This study reveals the important role of structural defects in tailoring and improving the charge transport properties of PdSe 2 .

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Section: ■ Results and Discussionmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Methodsmentioning

confidence: 99%

Section: Methodsmentioning

confidence: 99%

Section: ■ Experimental Sectionmentioning

confidence: 99%

See 3 more Smart Citations

Probing Intrinsic Defect-Induced Trap States and Hopping Transport in Two-Dimensional PdSe₂ Semiconductor Devices

Wang

Ali

Choi

et al. 2022

ACS Appl. Mater. Interfaces

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Achieving Ultrahigh Electron Mobility in PdSe₂ Field‐Effect Transistors via Semimetal Antimony as Contacts

Wang

Ali

Ngo

et al. 2023

Adv Funct Materials

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Even though atomically thin 2D semiconductors have shown great potential for next‐generation electronics, the low carrier mobility caused by poor metal–semiconductor contacts and the inherently high density of impurity scatterings remains a critical issue. Herein, high‐mobility field‐effect transistors (FETs) by introducing few‐layer PdSe2 flakes as channels is achieved, via directly depositing semimetal antimony (Sb) as drain–source electrodes. The formation of clean and defect‐free van der Waals (vdW) stackings at the Sb–PdSe2 heterointerfaces boosts the room temperature transport characteristics, including low contact resistance down to 0.55 kΩ µm, high on‐current density reaching 96 µA µm−1, and high electron mobility of 383 cm2 V−1 s−1. Furthermore, metal–insulator transition (MIT) is observed in the PdSe2 FETs with and without hexagonal boron nitride (h–BN) as buffer layers. However, the layered h–BN/PdSe2 vdW stacking eliminates the interference of interfacial disorders, and thus the corresponding device exhibits a lower MIT crossing point, larger mobility exponent of γ ∼ 1.73, significantly decreased hopping parameter of T0, and ultrahigh electron mobility of 2,184 cm2 V−1 s−1 at 10 K. These findings are expected to be significant for developing high mobility 2D‐based quantum devices.

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Self‐Assembly of Organic Semiconductors on Strained Graphene under Strain‐Induced Pseudo‐Electric Fields

Hwang,

Park,

Choi

et al. 2024

Advanced Science

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Graphene is used as a growth template for van der Waals epitaxy of organic semiconductor (OSC) thin films. During the synthesis and transfer of chemical‐vapor‐deposited graphene on a target substrate, local inhomogeneities in the graphene—in particular, a nonuniform strain field in the graphene template—can easily form, causing poor morphology and crystallinity of the OSC thin films. Moreover, a strain field in graphene introduces a pseudo‐electric field in the graphene. Here, the study investigates how the strain and strain‐induced pseudo‐electric field of a graphene template affect the self‐assembly of π‐conjugated organic molecules on it. Periodically strained graphene templates are fabricated by transferring graphene onto an array of nanospheres and then analyzed the growth and nucleation behavior of C60 thin films on the strained graphene templates. Both experiments and a numerical simulation demonstrated that strained graphene reduced the desorption energy between the graphene and the C60 molecules and thereby suppressed both nucleation and growth of the C60. A mechanism is proposed in which the strain‐induced pseudo‐electric field in graphene modulates the binding energy of organic molecules on the graphene.

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Interlayer electron modulation in van der Waals heterostructures assembled by stacking monolayer MoS₂ onto monolayer graphene with different electron transfer ability

Abstract: Achieving tunable optoelectronic properties and clarifying interlayer interactions are key challenges in the development of 2D heterostructures. Herein, we report the feasible modulation of the optoelectronic properties of monolayer MoS2...

Cited by 8 publications

References 46 publications

Probing Intrinsic Defect-Induced Trap States and Hopping Transport in Two-Dimensional PdSe₂ Semiconductor Devices

Probing Intrinsic Defect-Induced Trap States and Hopping Transport in Two-Dimensional PdSe₂ Semiconductor Devices

Achieving Ultrahigh Electron Mobility in PdSe₂ Field‐Effect Transistors via Semimetal Antimony as Contacts

Self‐Assembly of Organic Semiconductors on Strained Graphene under Strain‐Induced Pseudo‐Electric Fields

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Interlayer electron modulation in van der Waals heterostructures assembled by stacking monolayer MoS2 onto monolayer graphene with different electron transfer ability

Abstract: Achieving tunable optoelectronic properties and clarifying interlayer interactions are key challenges in the development of 2D heterostructures. Herein, we report the feasible modulation of the optoelectronic properties of monolayer MoS2...

Cited by 8 publications

References 46 publications

Probing Intrinsic Defect-Induced Trap States and Hopping Transport in Two-Dimensional PdSe2 Semiconductor Devices

Probing Intrinsic Defect-Induced Trap States and Hopping Transport in Two-Dimensional PdSe2 Semiconductor Devices

Achieving Ultrahigh Electron Mobility in PdSe2 Field‐Effect Transistors via Semimetal Antimony as Contacts

Self‐Assembly of Organic Semiconductors on Strained Graphene under Strain‐Induced Pseudo‐Electric Fields

Contact Info

Product

Resources

About

Interlayer electron modulation in van der Waals heterostructures assembled by stacking monolayer MoS₂ onto monolayer graphene with different electron transfer ability

Probing Intrinsic Defect-Induced Trap States and Hopping Transport in Two-Dimensional PdSe₂ Semiconductor Devices

Probing Intrinsic Defect-Induced Trap States and Hopping Transport in Two-Dimensional PdSe₂ Semiconductor Devices

Achieving Ultrahigh Electron Mobility in PdSe₂ Field‐Effect Transistors via Semimetal Antimony as Contacts