Probing Intrinsic Defect-Induced Trap States and Hopping Transport in Two-Dimensional PdSe₂ Semiconductor Devices

Abstract

Palladium diselenide (PdSe 2 ), as an emerging twodimensional (2D) layered material, is gaining growing attention in nanoelectronics and optoelectronics due to its thickness-dependent band gap, high carrier mobility, and good air stability. However, its asymmetric pentagon structure is inclined to breed defects. Herein, the intrinsic Se vacancy-induced trap states and their influence on the hopping transport in PdSe 2 are systematically investigated. We provide direct evidence that Se vacancies exist in the fresh PdSe 2 samples, which results in the localized trapping states inside the band gap. For the few-layer PdSe 2 , at 77 K, the trap density (D it ) near the midgap is about 2.2 × 10 13 cm −2 eV −1 , whereas at 295 K, the D it value increases to ∼7.1 × 10 13 cm −2 eV −1 . By comparison, the multilayer PdSe 2 shows nonobvious temperature-dependent trap behaviors with almost unchanged D it values of ∼8.1 × 10 12 cm −2 eV −1 at midgap in the temperature range between 77 and 295 K. Thus, trap states in the few-layer PdSe 2 are more vulnerable to temperature effect. Transport measurements demonstrated that both few-layer and multilayer PdSe 2 field-effect transistor (FET) devices show n-type dominant ambipolar behaviors. The electron mobility in the multilayer PdSe 2 FET is nearly 15-fold higher than that in the few-layer PdSe 2 FET at 315 K, probably owing to the decreased effective mass and suppression of charge impurity scattering in the thicker channel material. However, both FET devices exhibit variable-range hopping over a temperature range from 77 to 240 K and thermally activated hopping at temperatures above 240 K. The hopping transport mechanism is strongly associated with the Se vacancy-induced localized states with poor screening and strong potential fluctuations. This study reveals the important role of structural defects in tailoring and improving the charge transport properties of PdSe 2 .

Nanoscale Probing of Electrical Memory Effects in van der Waals Layered PdSe2

“…Complementary to prior findings on layer-and frequencydependent n-type dominated ambipolar capacitive behavior measured macroscopically by Wang et al, 23 we demonstrate that, on the nanoscale, capacitive and resistive characteristics can vary spatially and show varying degrees of charge inversion as well as hysteretic behavior. The observed hysteretic behavior can likely be ascribed to Se vacancy migration and switching of charge states, 19,26 as discussed above.…”

“…In metal oxide semiconductors, this important parameter indicates the voltage at which a conductive state is achieved and is dependent on the number of available charge carriers that are able to move under an applied electric field . Charge trapping impacts both the charge availability and transport and should therefore be reflected in the position of the minimum and the measured capacitance. ,, The behavior observed in Figure b is hysteretic, with the capacitance minimum after accumulation (green curve, minimum 1) occurring at a more negative voltage than the depletion after inversion (purple curve, minimum 2). The SMIM-C value of these minima can vary too.…”

“…31 Charge trapping impacts both the charge availability and transport and should therefore be reflected in the position of the minimum and the measured capacitance. 23,31,32 The behavior observed in Figure 2b is hysteretic, with the capacitance minimum after accumulation (green curve, minimum 1) occurring at a more negative voltage than the depletion after inversion (purple curve, minimum 2). The SMIM-C value of these minima can vary too.…”

“…The SMIM-C loop features some of the same characteristics as macroscopically measured capacitance−voltage curves and points to the previously reported ambipolar conductivity with dominant n-type charge carriers. 23,30 The increase in capacitance at positive voltages corresponds to the accumulation of n-type charge carriers, whereas the dip in SMIM-C at low negative voltages is associated with charge carrier depletion. This depletion phenomenon is detectable in SMIM because of a relatively small depletion length of ∼15 nm, 24 which is below the thickness of the NSs.…”

“…In this work, we investigate the local electrical and electronic properties of two-dimensional PdSe 2 . This material has attracted significant attention due to its unique pentagonal building blocks and highly anisotropic structures that induced many interesting properties such as air stability, high mobility, and n-type dominated ambipolar behavior. − Moreover, resistive switching has been observed in lateral and vertical geometries using macroscopic electrodes. , On the atomic scale, scanning tunneling microscopy showed that Se vacancies can be created, moved, and erased by applying electric fields, and their charge states can be switched between neutral and negative . However, little is known about the local capacitive and resistive behavior of PdSe 2 nanosheets (NSs) on mesoscopic lateral scales as well as the role of stacking on the electrical behavior.…”