Interference Analysis of Multicore Shared Resources with a Commercial Avionics RTOS

Park, Sihyeong; Song, Dae-Young; Jang, Hyeoksoo; Kwon, Mi-Young; Lee, Sang-Hun; Kim, Hoonkyu; Kim, Hyungshin

doi:10.1109/dasc43569.2019.9081704

Cited by 4 publications

(7 citation statements)

References 7 publications

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“…In 2019, Park et al [38] proposed an approach to reduce inter-core interference by applying the Time Division Multiple Access (TDMA) [169] and Acquisition-Execution-(AER) [172] execution models without modifying the Operating System. For the application of the execution models, they use pseudo-partitions.…”

Section: ) Hardware Isolationmentioning

confidence: 99%

A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore Platforms

et al. 2022

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This survey reviews the scientific literature on techniques for reducing interference in real-time multicore systems, focusing on the approaches proposed between 2015 and 2020. It also presents proposals that use interference reduction techniques without considering the predictability issue. The survey highlights interference sources and categorizes proposals from the perspective of the shared resource. It covers techniques for reducing contentions in main memory, cache memory, a memory bus, and the integration of interference effects into schedulability analysis. Every section contains an overview of each proposal and an assessment of its advantages and disadvantages.INDEX TERMS Real-time systems, architecture, multicore, timing analysis, schedulability analysis, WCET, co-runner interference.

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Section: ) Hardware Isolationmentioning

confidence: 99%

A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore Platforms

et al. 2022

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“…This section describes the results of measuring the interference due to memory sharing between cores by executing TDMA, AER, and multi-TDMA on the target hardware described in Section 3. Moreover, we describe the benchmark [15] for this experiment. Figure 11 shows the NXP T2080QDS board (NXP, Eindhoven, Netherlands) used to measure the memory sharing interference between cores.…”

Section: Evaluationsmentioning

confidence: 99%

“…We experimented with the TDMA, AER, and multi-TDMA models applied the micro-benchmarks proposed in the previous study [15]. The benchmark followed the phase structure of the AER model described in Section 3.2.2, implemented with one main function and each phase function.…”

Section: Benchmarkmentioning

confidence: 99%

“…Furthermore, we proposed a multi-TDMA model that considers the characteristics of the bus interface of the target board. Thus, we measured interference according to shared memory content with the benchmark proposed in our previous study [15]. In the preliminary study [15], we analyzed the memory interference according to the computational characteristics with MiBench automotive suite [16].…”

Section: Introductionmentioning

confidence: 99%

“…Thus, we measured interference according to shared memory content with the benchmark proposed in our previous study [15]. In the preliminary study [15], we analyzed the memory interference according to the computational characteristics with MiBench automotive suite [16]. To measure interference, we measured the execution time, the L1 and L2 cache miss, and the bus interface unit (BIU) requests during benchmark executions.…”

Section: Introductionmentioning

confidence: 99%

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Execution Model to Reduce the Interference of Shared Memory in ARINC 653 Compliant Multicore RTOS

et al. 2020

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Multicore architecture is applied to contemporary avionics systems to deal with complex tasks. However, multicore architectures can cause interference by contention because the cores share hardware resources. This interference reduces the predictable execution time of safety-critical systems, such as avionics systems. To reduce this interference, methods of separating hardware resources or limiting capacity by core have been proposed. Existing studies have modified kernels to control hardware resources. Additionally, an execution model has been proposed that can reduce interference by adjusting the execution order of tasks without software modification. Avionics systems require several rigorous software verification procedures. Therefore, modifying existing software can be costly and time-consuming. In this work, we propose a method to apply execution models proposed in existing studies without modifying commercial real-time operating systems. We implemented the time-division multiple access (TDMA) and acquisition execution restitution (AER) execution models with pseudo-partition and message queuing on VxWorks 653. Moreover, we propose a multi-TDMA model considering the characteristics of the target hardware. For the interference analysis, we measured the L1 and L2 cache misses and the number of main memory requests. We demonstrated that the interference caused by memory sharing was reduced by at least 60% in the execution model. In particular, multi-TDMA doubled utilization compared to TDMA and also reduced the execution time by 20% compared to the AER model.

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FlyOS: rethinking integrated modular avionics for autonomous multicopters

Farrukh

West

2023

Real-Time Syst

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Interference Analysis of Multicore Shared Resources with a Commercial Avionics RTOS

Cited by 4 publications

References 7 publications

A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore Platforms

A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore Platforms

Execution Model to Reduce the Interference of Shared Memory in ARINC 653 Compliant Multicore RTOS

FlyOS: rethinking integrated modular avionics for autonomous multicopters

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