Interfacial studies of Al<sub>2</sub>O<sub>3</sub> deposited on 4H‐SiC(0001)

Diplas, Spyros; Avice, Marc; Thøgersen, Annett; Christensen, J. S.; Großner, Ulrike; Svensson, B. G.; Nilsen, Ola; Fjellvåg, Helmer; Hinder, Steven J.; Watts, John F.

doi:10.1002/sia.2787

Cited by 10 publications

(4 citation statements)

References 18 publications

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“…On the other hand, in N 2 annealed samples at 300 °C show significantly higher peak of Si 0 and relatively lower peak of Si +1 oxidation state, referring to the un-oxidized Si. Whereas, very low quantity of Si +2 and Si +3 is present which could have been formed during the deposition process as indicated by Zhang et al [5] and Diplas [6]. The absence of Si +4 demonstrates that SiO 2 is not formed due to the presence of N 2 during the annealing.…”

Section: Resultsmentioning

confidence: 95%

“…In recent years, the main focus in alternate dielectric search was on interface stability, easy process integration, and di electric constant value. The dielectrics investigated for this purpose are Al 2 O 3 [5][6][7], AlN [8], HfO 2 [9,10], Ta 2 O 5 [11], TiO 2 , etc and combinations of one or two dielectrics in layered form [9,14], as well as mixed form such as aluminum oxynitride (AlON) [15], Hf x Ti 1−x O 2 and Hf x Ti 1−x ON [13,16,17]. It is particularly important to note that most of the stacked and mixed dielectric efforts were made by adding thin SiO 2 as a first layer interfacing with 4H-SiC [18].…”

Section: Introductionmentioning

confidence: 99%

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Influence of annealing environment on the ALD-Al₂O₃/4H-SiC interface studied through XPS

Usman

Arshad

Suvanam

et al. 2018

J. Phys. D: Appl. Phys.

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The instability of Al2O3/4H-SiC interface at various process temperatures and ambient is investigated by the annealing of Al2O3/4H-SiC in low vacuum conditions as well as in N2 environments. Atomic layer deposited Al2O3 on a 4H-SiC substrate with 3, 6 and 10 nm of thicknesses is treated at 300, 500, 700 and 900 °C under the vacuum level of 10−1 torr. The as-deposited and annealed structures are analyzed using x-ray photoelectron spectroscopy. It is hypothesized that the minute quantity of oxygen present in low vacuum conditions diffuses through thin layers of Al2O3 and helps in forming SiO2 at the interface even at low temperatures (i.e. 300 °C), which plays a pivotal role in determining the electrical properties of the interface. It is also proved that the absence of oxygen in the ambient prevents the formation of SiO2 at low temperatures. Additionally, it is observed that Al–OH is present in as-deposited layers, which gradually reduces after annealing. However, at around 700 °C, the concentration of oxygen in the whole structure increases to maximum and reduces at 900 °C.

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Section: Resultsmentioning

confidence: 95%

Section: Introductionmentioning

confidence: 99%

Influence of annealing environment on the ALD-Al₂O₃/4H-SiC interface studied through XPS

Usman

Arshad

Suvanam

et al. 2018

J. Phys. D: Appl. Phys.

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“…Therefore, the reduction of D it s is a consequence of interface modification upon high temperature treatment probably resulting in the formation of thin SiO 2 interfacial layer. 20 It has previously been shown that the high temperature treatment of Al 2 O 3 interface with SiC significantly improves the quality of the interface in terms of charges and interface states. Therefore, it can be concluded that high temperature treatment of Al 2 O 3 interface with SiC will improve the quality of the interface and does not degrade it.…”

Section: Resultsmentioning

confidence: 99%

HfO₂/Al₂O₃Bilayered High-kDielectric for Passivation and Gate Insulator in 4H-SiC Devices

Usman

Henkel

Hallén

2013

ECS J. Solid State Sci. Technol.

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The electrical and chemical properties of high-k dielectric stacks consisting of Hafnium oxide (HfO 2 ) and Aluminum oxide (Al 2 O 3 ) deposited on 4H-SiC have been investigated by preparing metal insulator semiconductor (MIS) structures of HfO 2 /Al 2 O 3 /SiC. The bilayer gate stack was deposited by using atomic layer deposition (ALD). The samples were also treated by rapid thermal annealing (RTA) at 970 • C for 5 mins in an inert gas atmosphere. Structural properties of the deposited films were analyzed with X-ray diffraction (XRD), atomic force microscopy (AFM) and Rutherford backscattering spectroscopy (RBS). Capacitance-voltage (CV) measurements performed on as-deposited and RTA treated structures at room temperature show that the RTA treatment increases the effective oxide charges in the whole dielectric but decreases the interface trap density. Current-voltage (IV) measurements have been performed in order to extract the leakage current density as well as the breakdown characteristics of the stack. Our results show that a combination of HfO 2 and Al 2 O 3 can be a better choice for SiC than individual Al 2 O 3 layer because of the higher value of effective dielectric constant. It is shown that the stacked dielectrics are stable at high temperatures and under annealing conditions up to 300 • C, which makes the layers compatible with SiC device processing and higher operating temperatures compared to silicon.

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“…Hence, Al 2 O 3 deposited by atomic layer deposition (ALD) can only be used as a barrier in a very limited range of temper atures. Furthermore, several studies have shown that oxygen may react with SiC beneath Al 2 O 3 and form a thin layer of silicon oxide (SiO x , 1 ⩽ x ⩽ 2) at the interface [9][10][11].…”

Section: Introductionmentioning

confidence: 99%

Interface between Al₂O₃and 4H-SiC investigated by time-of-flight medium energy ion scattering

Linnarsson

Hallén

Khartsev

et al. 2017

J. Phys. D: Appl. Phys.

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The formation of interfacial oxides during heat treatment of dielectric films on 4H-SiC has been studied. The 4H-SiC surface has been carefully prepared to create a clean and abrupt interface to Al 2 O 3 . An amorphous, 3 nm thick, Al 2 O 3 film has been prepared on 4H-SiC by atomic layer deposition and rapid thermal annealing was then performed in N 2 O ambient at 700 °C and 1100 °C during 1 min. The samples were studied by time-of-flight medium energy ion scattering (ToF-MEIS), with sub-nanometer depth resolution and it is seen that, at both annealing temperatures, a thin SiO x (1 ⩽ x ⩽ 2) is formed at the interface. Our results further indicate that carbon remains in the silicon oxide in samples annealed at 700 °C. Additional electrical capacitance voltage measurements indicate that a large concentration of interface traps is formed at this temperature. After 1100 °C annealing, both MEIS and XRD measurements show that these features disappear, in accordance with electrical data.

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Interfacial studies of Al₂O₃ deposited on 4H‐SiC(0001)

Cited by 10 publications

References 18 publications

Influence of annealing environment on the ALD-Al₂O₃/4H-SiC interface studied through XPS

Influence of annealing environment on the ALD-Al₂O₃/4H-SiC interface studied through XPS

HfO₂/Al₂O₃Bilayered High-kDielectric for Passivation and Gate Insulator in 4H-SiC Devices

Interface between Al₂O₃and 4H-SiC investigated by time-of-flight medium energy ion scattering

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Interfacial studies of Al2O3 deposited on 4H‐SiC(0001)

Cited by 10 publications

References 18 publications

Influence of annealing environment on the ALD-Al2O3/4H-SiC interface studied through XPS

Influence of annealing environment on the ALD-Al2O3/4H-SiC interface studied through XPS

HfO2/Al2O3Bilayered High-kDielectric for Passivation and Gate Insulator in 4H-SiC Devices

Interface between Al2O3and 4H-SiC investigated by time-of-flight medium energy ion scattering

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Interfacial studies of Al₂O₃ deposited on 4H‐SiC(0001)

Influence of annealing environment on the ALD-Al₂O₃/4H-SiC interface studied through XPS

Influence of annealing environment on the ALD-Al₂O₃/4H-SiC interface studied through XPS

HfO₂/Al₂O₃Bilayered High-kDielectric for Passivation and Gate Insulator in 4H-SiC Devices

Interface between Al₂O₃and 4H-SiC investigated by time-of-flight medium energy ion scattering