Interfaces and Communication Protocols in ATCA-Based LLRF Control Systems

Makowski, Dariusz; Koprek, Waldemar; Jeżyński, Tomasz; Piotrowski, A.; Jablonski, Grzegorz; Jałmużna, Wojciech; Simrock, S.

doi:10.1109/tns.2009.2027234

“…From the point of view of the user, the various parameters and monitors are registers of variable width, mapped onto the PCI Express memory space. On the FPGA side, the registers are handled via the so-called Integral Interface (II) [17]. The Parameter and Monitor blocks in the Rapid-X library (Fig.…”

Section: B Parameter and Monitor Blocksmentioning

confidence: 99%

Rapid-X - An FPGA Development Toolset Using a Custom Simulink Library for MTCA.4 Modules

Prędki

¹

,

Heuer

²

,

Butkowski

³

et al. 2015

IEEE Trans. Nucl. Sci.

View full text Add to dashboard Cite

The recent introduction of advanced hardware architectures such as the Micro Telecommunications Computing Architecture (MTCA) caused a change in the approach to implementation of control schemes in many fields. The development has been moving away from traditional programming languages ( ), to hardware description languages (VHDL, Verilog), which are used in FPGA development. With MATLAB/Simulink it is possible to describe complex systems with block diagrams and simulate their behavior. Those diagrams are then used by the HDL experts to implement exactly the required functionality in hardware. Both the porting of existing applications and adaptation of new ones require a lot of development time from them. To solve this, Xilinx System Generator, a toolbox for MATLAB/Simulink, allows rapid prototyping of those block diagrams using hardware modelling. It is still up to the firmware developer to merge this structure with the hardware-dependent HDL project. This prevents the application engineer from quickly verifying the proposed schemes in real hardware. The framework described in this article overcomes these challenges, offering a hardware-independent library of components that can be used in Simulink/System Generator models. The components are subsequently translated into VHDL entities and integrated with a pre-prepared VHDL project template. Furthermore, the entire implementation process is run in the background, giving the user an almost one-click path from control scheme modelling and simulation to bit-file generation. This approach allows the application engineers to quickly develop new schemes and test them in real hardware environment. The applications may range from simple data logging or signal generation ones to very advanced controllers. Taking advantage of the Simulink simulation capabilities and user-friendly hardware implementation routines, the framework significantly decreases the development time of FPGA-based applications.

show abstract

“…The control data can be sent using both PCI Express or Gb Ethernet standards. More detailed discussion concerning data requirements and transmission in the LLRF system based on the ATCA standard can be found in [17]. In case of the distributed system, redundancy of main interfaces could be required [18].…”

Section: A Centralized Versus Distributed Llrf Systemmentioning

confidence: 99%

“…The carrier board provides all the necessary interfaces for the RT controller, system management and diagnostics required by the ATCA standard. A more detailed discussion of various links can be found in [17]. The FPGA device is connected using Low Latency Links (LLL) with all three AMC modules.…”

Section: Atca-based Llrf Control Systemmentioning

confidence: 99%

Prototype Real-Time ATCA-Based LLRF Control System

Makowski

¹

,

Koprek

²

,

Jeżyński

³

et al. 2011

IEEE Trans. Nucl. Sci.

Self Cite

View full text Add to dashboard Cite

Abstract-The linear accelerators employed to drive Free Electron Lasers (FELs), such as the X-ray Free Electron Laser (XFEL) currently being built in Hamburg, require sophisticated control systems. The Low Level Radio Frequency (LLRF) control system should stabilize the phase and amplitude of the electromagnetic field in accelerating modules with tolerances below 0.02 % for amplitude and 0.01 degree for phase to produce ultra-stable electron beam that meets the conditions required for Self-Amplified Spontaneous Emission (SASE). The LLRF control system of 32-cavity accelerating module of the XFEL accelerator requires acquisition of more than 100 analogue signals sampled with frequency around 100 MHz. Data processing in real-time loop should complete within a few hundreds of nanoseconds. Moreover, the LLRF control system should be reliable, upgradable and serviceable. The Advanced Telecommunications Computing Architecture (ATCA) standard, developed for telecommunication applications, can fulfil all of the above mentioned requirements.The paper presents the architecture of a prototype LLRF control system developed for the XFEL accelerator. The control system composed of ATCA carrier boards with Rear Transition Modules (RTM) is able to supervise 32 cavities. The crucial submodules, like DAQ, Vector Modulator or Timing Module, are designed according to AMC specification. The paper discusses results of the LLRF control system tests that were performed at the FLASH accelerator (DESY, Hamburg) during machine studies.

show abstract

“…A more detailed discussion of various links can be found in [17]. The FPGA device is connected using Low Latency Links (LLL) with all three AMC modules.…”

Section: Atca-based Llrf Control Systemmentioning

confidence: 99%

Prototype real-time ATCA-based LLRF control system

Makowski

¹

,

Koprek

²

,

Jezynski

³

et al. 2010

2010 17th IEEE-NPSS Real Time Conference

Self Cite

1

0

View full text Add to dashboard Cite

Abstract-The linear accelerators employed to drive Free Electron Lasers (FELs), such as the X-ray Free Electron Laser (XFEL) currently being built in Hamburg, require sophisticated control systems. The Low Level Radio Frequency (LLRF) control system should stabilize the phase and amplitude of the electromagnetic field in accelerating modules with tolerances below 0.02 % for amplitude and 0.01 degree for phase to produce ultra-stable electron beam that meets the conditions required for Self-Amplified Spontaneous Emission (SASE). The LLRF control system of 32-cavity accelerating module of the XFEL accelerator requires acquisition of more than 100 analogue signals sampled with frequency around 100 MHz. Data processing in real-time loop should complete within a few hundreds of nanoseconds. Moreover, the LLRF control system should be reliable, upgradable and serviceable. The Advanced Telecommunications Computing Architecture (ATCA) standard, developed for telecommunication applications, can fulfil all of the above mentioned requirements.The paper presents the architecture of a prototype LLRF control system developed for the XFEL accelerator. The control system composed of ATCA carrier boards with Rear Transition Modules (RTM) is able to supervise 32 cavities. The crucial submodules, like DAQ, Vector Modulator or Timing Module, are designed according to AMC specification. The paper discusses results of the LLRF control system tests that were performed at the FLASH accelerator (DESY, Hamburg) during machine studies.

show abstract

Interfaces and Communication Protocols in ATCA-Based LLRF Control Systems

Cited by 8 publications

References 8 publications

Rapid-X - An FPGA Development Toolset Using a Custom Simulink Library for MTCA.4 Modules

Rapid-X - An FPGA Development Toolset Using a Custom Simulink Library for MTCA.4 Modules

Prototype Real-Time ATCA-Based LLRF Control System

Prototype real-time ATCA-based LLRF control system

Contact Info

Product

Resources

About