Interface Trap Generation and Hole Trapping Under NBTI and PBTI in Advanced CMOS Technology With a 2-nm Gate Oxide

Denais, M.; Huard, V.; Parthasarathy, C.; Ribes, G.; Perrier, F.; Revil, N.; Bravaix, A.

doi:10.1109/tdmr.2004.840856

Cited by 110 publications

(51 citation statements)

References 28 publications

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“…4) practically no hysteresis is introduced (no NBTI stress) and also the oxide trap contribution is reduced, consistent with the idea that these traps are due to a thermally activated tunneling mechanism [16] rather than elastic (and thus temperature-independent) hole tunneling [1].…”

Section: E Lower Temperaturesupporting

confidence: 77%

“…Experimental differentiation between oxide and interface states is extremely challenging due to the rapid recovery of the degradation setting in as soon as the stress is removed. In particular, it has been observed that when after NBTI stress the device is positively biased, a considerable part of the recoverable component is lost [1][2][3][4]. Until recently, this has been explained by the detrapping of holes [2,3], while interface states have been assumed to only change their occupancy but do not recover.…”

Section: Introductionmentioning

confidence: 99%

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Do NBTI-induced interface states show fast recovery? A study using a corrected on-the-fly charge-pumping measurement technique

Hehenberger

Aichinger²,

Grasser

et al. 2009

2009 IEEE International Reliability Physics Symposium

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Abstract-Data obtained by the recently developed on-the-fly chargepumping technique has suggested a fast initial degradation and recovery of interface states during negative and/or bias temperature stress, contrary to previously published results. By revising the analysis of the measurement setup, fast interface state creation and recovery are revealed as artifact due to a different amount of oxide traps seen during the stress and relaxation phases. From this analysis we conclude that data gathered during stress and recovery phases must not be directly compared. By properly taking the contribution of (slow) oxide charges into account, which leads to a spurious increase of the charge-pumping current during the stress phase, we demonstrate that no fast initial degradation and no fast recovery of interface states occurs. Nevertheless, the charge-pumping signal is sensitive to the continuous switching of the gate voltage into accumulation, which also accelerates interface state recovery, albeit at a slower rate. We finally conclude that both the fast initial degradation and the fast initial recovery seem to be due to oxide charges. Therefore these oxide charges need to be considered. By performing simulations with our device simulator Minimos-NT using a modified Shockley-ReadHall model it was possible to reproduce the effect of these oxide charges. For this purpose a temperature and field activated tunneling process is assumed and results in proper agreement of measurement and simulation. A correction scheme for the on-the-fly charge-pumping measurement technique is then presented.

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Section: E Lower Temperaturesupporting

confidence: 77%

Section: Introductionmentioning

confidence: 99%

Do NBTI-induced interface states show fast recovery? A study using a corrected on-the-fly charge-pumping measurement technique

Hehenberger

Aichinger²,

Grasser

et al. 2009

2009 IEEE International Reliability Physics Symposium

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show abstract

“…An overview of NBTI and other aging effects can be seen in [36]. NBTI may increase the theshold voltage (VTH) of the PMOS transistors subjected to negative gate to source bias due to high temperature stress conditions [37]- [38]. If the preferred start-up value of a cell is stored during a long time, the PMOS transistor with smaller VTH is turned on and its VTH may increase because of NBTI degradation.…”

Section: E Advantages For Countering Agingmentioning

confidence: 99%

Improved Generation of Identifiers, Secret Keys, and Random Numbers From SRAMs

Baturone

Prada-Delgado

Eiroa³

2015

IEEE Trans.Inform.Forensic Secur.

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Abstract-This paper presents a method to simultaneously improve the quality of the identifiers, secret keys, and random numbers that can be generated from the start-up values of standard Static Random Access Memories, SRAMs. The method is based on classifying memory cells after evaluating their startup values at multiple measurements in a registration phase. The registration can be done without unplugging the device from its application context, and with no need for a complex laboratory setup. The method has been validated experimentally with standard low-power SRAM modules in two different Application Specific Integrated Circuits, ASICs, fabricated with 90-nm TSMC technology. The results show that with a simple registration the length of the identifiers can be reduced by 45%, worst-case bit error probability (which defines the complexity of the error correcting code needed to recover a secret key) can be reduced by 64%, and the worst-case minimum entropy value is improved, thus reducing the number of bits that have to be processed to obtain full entropy by 81%. The method can be applied to standard digital designs by controlling the external power supply to the SRAM using software or by incorporating simple circuitry in the design. In the latter case, a module for implementing the method in an ASIC designed in 90-nm TSMC technology occupies an active area of 42,025 μm 2 .

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“…However continuous push for smaller devices and interconnects has moved the technology closer to a point of unreliability where such design paradigm is not valid [9]- [11]. For example, at 90nm technology Negative Bias Temperature Instability (NBTI), where a PMOS device degrades continuously with voltage and temperature stress, had become a major reliability concern, [12]- [13]. At 45nm, the problem has exacerbated due to lower threshold voltage, and Positive Bias Temperature Instability (PBTI) for NMOS devices has been added to the list [12].…”

Section: Yieldmentioning

confidence: 99%

A Hardware Framework for Yield and Reliability Enhancement in Chip Multiprocessors

Pan

Rodrigues

Kundu

2015

ACM Trans. Embed. Comput. Syst.

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Device reliability and manufacturability have emerged as dominant concerns in end-of-road CMOS devices. An increasing number of hardware failures are attributed to manufacturability or reliability problems. Maintaining an acceptable manufacturing yield for chips containing tens of billions of transistors with wide variations in device parameters has been identified as a great challenge. Additionally, today’s nanometer scale devices suffer from accelerated aging effects because of the extreme operating temperature and electric fields they are subjected to. Unless addressed in design, aging-related defects can significantly reduce the lifetime of a product. In this article, we investigate a micro-architectural scheme for improving yield and reliability of homogeneous chip multiprocessors (CMPs). The proposed solution involves a hardware framework that enables us to utilize the redundancies inherent in a multicore system to keep the system operational in the face of partial failures. A micro-architectural modification allows a faulty core in a CMP to use another core’s resources to service any instruction that the former cannot execute correctly by itself. This service improves yield and reliability but may cause loss of performance. The target platform for quantitative evaluation of performance under degradation is a dual-core and a quad-core chip multiprocessor with one or more cores sustaining partial failure. Simulation studies indicate that when a large, high-latency, and sparingly used unit such as a floating-point unit fails in a core, correct execution may be sustained through outsourcing with at most a 16% impact on performance for a floating-point intensive application. For applications with moderate floating-point load, the degradation is insignificant. The performance impact may be mitigated even further by judicious selection of the cores to commandeer depending on the current load on each of the candidate cores. The area overhead is also negligible due to resource reuse.

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Interface Trap Generation and Hole Trapping Under NBTI and PBTI in Advanced CMOS Technology With a 2-nm Gate Oxide

Cited by 110 publications

References 28 publications

Do NBTI-induced interface states show fast recovery? A study using a corrected on-the-fly charge-pumping measurement technique

Do NBTI-induced interface states show fast recovery? A study using a corrected on-the-fly charge-pumping measurement technique

Improved Generation of Identifiers, Secret Keys, and Random Numbers From SRAMs

A Hardware Framework for Yield and Reliability Enhancement in Chip Multiprocessors

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