Interface state generation under long-term positive-bias temperature stress for a p/sup +/ poly gate MOS structure

Abstract

Abstraet-Long-term reliability for a p+ poly gate MOS structure was tested under low electric field bias temperature (BT) stress in comparison with an n+ poly gate. A significant increase in interface state density was observed for the pf poly gate MOS structure under positive bias conditions. This phenomenon was not observed in the n + poly gate case. The mechanism for this interface state increase was investigated in detail. Several possible causes, such as mobile ions, excess boron concentration in the gate oxide, electron injection from the substrate, impact ionization in the gate oxide, and bole injection from the gate electrode, were considered. All of the causes, except hole injection, were obviated by experiments. Although hole injection current was too small to be detected, hole injection from the p+ poly gate is a possible cause, which could explain the interface state generation under positive-bias temperature test. For applying a p+ poly gate to CMOS structures, care should be taken when positive bias is applied to the gate electrode.

Behavior of hot hole stressedSiO2/Si interface at elevated temperature

“…10 It has been reported that the trapped holes can also induce slow states 11 and the hole injection can enhance the positive bias temperature instability for metal-oxide-semiconductor field effect transistors ͑MOSFETs͒ with pϩ poly-Si gate. 9 After hole injection is terminated, the generation of interface states can continue. 1,13 This post-stress degradation reduces device lifetime 1 and its physical mechanism is still not clear.…”

“…However, instabilities can be induced both in the bulk of SiO 2 and at the SiO 2 /Si interface under a number of stress conditions, such as hot carrier injection, [1][2][3] Fowler-Nordheim injection, 4 irradiation, [5][6][7] and bias temperature stress. 8,9 Damages can be caused by both electrons and holes. This article focuses on the latter.…”

Current increase in thin gate-oxide (3.5–7.0 nm) metal–oxide–silicon structures with the boron-doped polycrystalline-silicon gates biased negatively

“…Neugebauer et al 14 reported current decay for both positive and negative gate biases. Hiruta et al, 15 Ushizaka and Sato 16 and Abadeer et al 17 showed that the interface-state density at the Si-SiO 2 interface increases when the gate is biased positively. These instabilities are summarized in Table III.…”

“…Neugebauer et al 14 reported current decay for both positive and negative gate bias. Hiruta et al 15 found that the interface-state density at the Si-SiO 2 interface increases when the gate is biased positively. Ushizaka and Sato 16 and Abadeer et al 17 discussed the interface-state density increase in detail.…”

“…[4][5][6][7][8][9][10][11] Many investigators have reported various instabilities related to boron-doped poly-silicon gate MOS structures. [12][13][14][15][16][17] Faggin et al 12 showed that the threshold voltage of MOS transistors shifts negatively when the gate voltage is positively biased. This negative shift ͑instability͒ was explained by Nakayama et al 13 as the effect of ethyl alcohol or acetone.…”