Interface properties of thin oxides grown on strained GexSi1−x layer

Abstract

The electrical and chemical properties of the interfaces of thin oxides grown on strained GexSi1−x layers are analyzed in detail using capacitance-voltage measurements and Auger electron spectroscopy. It is found that the electrical properties (interface states and fixed oxide charges) of the interface depend on various parameters such as oxidation temperature, oxidation time, Ge distribution near the interface, and Ge distribution in the entire epilayer. The Ge distribution at the interface can be described using concentration-dependent diffusivity of Ge in the epilayer. The electrical properties are improved with the increase in oxidation temperature, but for a given oxidation temperature, the quality of the interface degrades with the increase in oxidation time. At a very high oxidation temperature the Ge distribution in the entire epilayer is altered due to the high diffusivity of Ge.

Impact of carbon concentration on the interface density of states of metal-oxide Si1−x−y GexCy (strained) capacitors

“…6 However, the use of Si 1-x Ge x in complementary metal-oxide semiconductor (CMOS) technology has been hindered by the reduced quality of the oxide/epilayer interface. [7][8][9] The benefits of Si 1-x Ge x for CMOS devices rely primarily on increased carrier mobility in comparison to Si and the possibility to master the whole band structure to give superior device performance. 1,4 However, its metastability, caused by the lattice mismatch with the substrate, prevents the production of epilayers with high structural quality unless suitable buffer layers with graded composition are grown.…”

Liquid phase deposition silicon dioxide for surface passivation in SiGe metal-semiconductor-metal photodetectors

“…From our C-V-measurements, the interface states that density between SiGe and LPD-oxide layer was about 3 × 10 11 cm − 2 eV − 1 for non-annealed LPD. This value is lower than that (N 10 12 cm − 2 eV − 1 ) of thermal oxide on SiGe films [23]. Fig.…”

Charge-trap memory device fabricated by oxidation of Si/sub 1-x/Ge/sub x/

“…The size to the Ge nanocrystals in the fabricated devices is estimated to be less than 25 Å. A small amount of Ge remains at the interface, creating interface traps and thereby degrading the transistor performance [16]. Nitrogen implantation followed by high-temperature annealing was employed to passivate the Ge.…”