Interface engineering for highly-reliable 65 nm-node Cu/ULK (k=2.6) interconnect integration

Ishii, Atsushi; Matsumoto, Susumu; Hattori, Tatsuya; Suzuki, Shigeru; Isono, S.; Iwasaki, Atsushi; Tomita, Kazuo; Hashimoto, Kohei; Tawa, S.; Furusawa, Takeshi; Kodama, Daisuke; Ogawa, S.; Suzumura, S.; Tsutsue, M.; Goto, Kazuya; Kobayashi, Kojiro; Ohshita, Hideki; Hamada, Mototsugu; Amoh, N.; Okamura, H.; Yonekura, Kazumasa; Hamatani, Tsuyoshi; Kobayshi, T.; Tsukamoto, Kazuyoshi; Matsuura, M.

doi:10.1109/iitc.2005.1499910

Cited by 2 publications

(3 citation statements)

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“…The SiCO- or SiCN-base films on a copper layer have been widely used in the copper dual damascene process as a copper ion barrier layer [ 9 , 10 ]. Moreover the influences of the etching-stop-layer, silicon carbide (SiC) barrier cap layer, and deposition process on electro migration (EM) and stress migration (SM) have been reported [ 4 , 11 ]. The copper and barrier layer interface is the dominant path for copper migration [ 5 , 11 , 12 ].…”

Section: Methodsmentioning

confidence: 99%

“…For example, a Cu film is easily oxidized, and Cu atoms or ions easily diffuse into low k interlayer dielectrics by thermal annealing or with electric fields [ 3 ]. Thus, it is desirable to develop new materials with a lower k -value to further reduce the effective dielectric constant of the Cu interconnect system [ 4 , 5 ]. It is also known that Cu is a serious source of contamination for both silicon and silicon dioxide.…”

Section: Introductionmentioning

confidence: 99%

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A Study of Trimethylsilane (3MS) and Tetramethylsilane (4MS) Based α-SiCN:H/α-SiCO:H Diffusion Barrier Films

Chen

Wang

et al. 2012

Materials

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Amorphous nitrogen-doped silicon carbide (α-SiCN:H) films have been used as a Cu penetration diffusion barrier and interconnect etch stop layer in the below 90-nanometer ultra-large scale integration (ULSI) manufacturing technology. In this study, the etching stop layers were deposited by using trimethylsilane (3MS) or tetramethylsilane (4MS) with ammonia by plasma-enhanced chemical vapor deposition (PECVD) followed by a procedure for tetra-ethoxyl silane (TEOS) oxide. The depth profile of Cu distribution examined by second ion mass spectroscopy (SIMs) showed that 3MS α-SiCN:H exhibited a better barrier performance than the 4MS film, which was revealed by the Cu signal. The FTIR spectra also showed the intensity of Si-CH3 stretch mode in the α-SiCN:H film deposited by 3MS was higher than that deposited by 4MS. A novel multi structure of oxygen-doped silicon carbide (SiC:O) substituted TEOS oxide capped on 4MS α-SiC:N film was also examined. In addition to this, the new multi etch stop layers can be deposited together with the same tool which can thus eliminate the effect of the vacuum break and accompanying environmental contamination.

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Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Study of Trimethylsilane (3MS) and Tetramethylsilane (4MS) Based α-SiCN:H/α-SiCO:H Diffusion Barrier Films

Chen

Wang

et al. 2012

Materials

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“…In the actual CMP process with Cu patterned wafers, care must be taken regarding the removal of Cu-organic complex residue during the post-CMP cleaning. 6,7) In this section, two types of rinse solutions are compared: DIW and alkaline water with an ORP maintained at about À0:7 V vs NHE.…”

Section: Post-cmp Cleaning On Low-k /Cu Interconnectsmentioning

confidence: 99%

Defectless Monolithic Low-k/Cu Interconnects Produced by Chemically Controlled Chemical Mechanical Polishing Process with In situ End-Point-Detection Technique

Ueki¹,

Onodera²,

Ishikawa

et al. 2009

jjap

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Defectless monolithic low-k /Cu interconnects have been obtained for low-power LSIs by a chemically controlled local chemical mechanical polishing (CMP) process to remove a Cu/TaN barrier on hydrophobic SiOCH low-k films. In the first step, Cu-CMP, a unique end-pointdetection (EDP) method is implemented to detect a very thin Cu layer ($100 nm) that remains on the TaN barrier by in situ white-light interferometry, which is implemented in the local CMP apparatus where the wafers undergoing polishing are oriented face-up. In the second step, TaN-CMP, a SiO 2 hard-mask (HM) layer on the low-k film is selectively removed to reduce the nonuniformity of the Cu line thickness, and accordingly, those of the resistance and capacitance. Here, a CMP slurry with an oxidizer is used to change the low-k surface from a hydrophobic condition to a hydrophilic condition, improving wettability and reducing the number of scratches and abrasive particles. In the post-CMP cleaning, an alkaline rinse solution with an oxidation-reduction potential (ORP) of less than À0:5 V vs a normal hydrogen electrode (NHE) produces a clean low-k surface resulting in monolithic low-k /Cu interconnects with excellent dielectric properties comparable to those of SiO 2 /Cu interconnects.

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Interface engineering for highly-reliable 65 nm-node Cu/ULK (k=2.6) interconnect integration

Cited by 2 publications

References 0 publications

A Study of Trimethylsilane (3MS) and Tetramethylsilane (4MS) Based α-SiCN:H/α-SiCO:H Diffusion Barrier Films

A Study of Trimethylsilane (3MS) and Tetramethylsilane (4MS) Based α-SiCN:H/α-SiCO:H Diffusion Barrier Films

Defectless Monolithic Low-k/Cu Interconnects Produced by Chemically Controlled Chemical Mechanical Polishing Process with In situ End-Point-Detection Technique

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