Interface-Engineered Ge (100) and (111), N- and P-FETs with High Mobility

Kuzum, Duygu; Pethe, Abhijit; Krishnamohan, Tejas; Oshima, Yasuhiro; Sun, Yun; McVittie, J.P.; Pianetta, P.; Mclntyre, P.C.; Saraswat, Krishna C.

doi:10.1109/iedm.2007.4419048

Cited by 65 publications

(60 citation statements)

References 6 publications

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“…Possible alternatives include Ge, GaAs, InGaAs, InAs, InSb, GaN, and perhaps others [2][3][4][5][6][7][8]. Recently published results from high performance flatband-mode [9] In 0.3 Ga 0.7 As channel enhancement-mode MOSFETs on GaAs substrate conclusively demonstrate that the historical issue of Fermi-level pinning at the GaAs/dielectric interface can be overcome [10].…”

mentioning

confidence: 94%

1 [micro sign]m gate length, In0.75Ga0.25As channel, thin body n-MOSFET on InP substrate with transconductance of 737 [micro sign]S/μm

Hill

Droopad²,

Moran

et al. 2008

Electron. Lett.

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mentioning

confidence: 94%

1 [micro sign]m gate length, In0.75Ga0.25As channel, thin body n-MOSFET on InP substrate with transconductance of 737 [micro sign]S/μm

Hill

Droopad²,

Moran

et al. 2008

Electron. Lett.

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“…As for the gate insulators or interfacial control layers with Ge, various films including GeO 2 , [1][2][3][4][5][6][7][8][9][10][11] GeON, 4,6,12,13) and Ge 3 N 4 3, [14][15][16][17] have already been reported. Among them, GeO 2 / Ge interfaces have recently been reported to provide lowdensity interface defects and high-performance MOSFETs under a variety of fabrication processes.…”

Section: Introductionmentioning

confidence: 99%

Interface-Controlled Self-Align Source/Drain Ge p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors Fabricated Using Thermally Oxidized GeO₂Interfacial Layers

Nakakita

Nakakne

Sasada

et al. 2011

Jpn. J. Appl. Phys.

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We have successfully fabricated high hole mobility Ge p-channel metal-oxide-semiconductor field-effect transistors (p-MOSFETs) with GeO 2 /Ge formed by direct thermal oxidation, which can yield a significantly low interface trap density (D it ). Al 2 O 3 films are employed as capping layers for protecting the GeO 2 /Ge MOS interfaces during the MOSFET fabrication processes. The source/drain (S/D) regions are formed by boron ion implantation in a self-align way with Al gate metal. The good MOS interface properties are found to be maintained even after the activation annealing at temperatures sufficient for obtaining the excellent junction properties. The fabricated MOSFETs exhibit high source and drain on/off current ratios of 10 5 -10 4 and a high peak hole mobility of 575 cm 2 V À1 s À1 at maximum, both of which are attributable to the excellent GeO 2 /Ge MOS interface properties. The effects of the substrate impurity concentration and the thickness of GeO 2 on the hole mobility are examined. It is found from the results for different substrate impurity concentrations that the universal curve between hole mobility and the effective field E eff holds for ¼ 1=3. We also investigate the impact of the oxidation temperature dependence on hole mobility in order to examine the scattering mechanism limiting the mobility of GeO 2 /Ge interfaces through the modulation of the MOS interfaces by changing oxidation temperature. It is found that the mobility in low-temperature and low-surface carrier density (N s ) regions is well corrected with D it evaluated from S factors in MOSFETs. In addition, it is revealed from transmission electron microscopy analyses that the interface roughness between GeO 2 and Ge is reduced with increasing oxidation temperature. From these experimental results, the higher mobility of GeO 2 /Ge p-MOSFET at higher oxidation temperatures can be explained by the reduction in the density of Coulomb scattering centers and surface roughness at elevated Ge oxidation temperatures. #

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“…In particular, GeO 2 /Ge interfaces have been reported to provide superior interface properties [7,8,[15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30]. Actually, high performance n-and pMOSFETs with this GeO 2 /Ge interface control layer have already been demonstrated by many research groups [8,18,19,22,[24][25][26][27][28][29][30]. However, co-existence of thin EOT and low D it is still a challenging issue for this interfacial layer.…”

Section: Introductionmentioning

confidence: 99%

“…The other direction is double layer gate stacks composed of high k layers and intentionally-formed interface control layers. A variety of interfacial layers such as SiO 2 /Si [10][11][12][13][14], GeO 2 [7,8,[15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30], GeON [19,[31][32][33] and Ge 3 N 4 [16,[34][35][36][37] have already been reported. Although the introduction of interfacial low k layers could lead to the increase in EOT, superior interface properties to provide high inversion-layer mobility can be expected, as similar with the high k/SiO 2 /Si system.…”

Section: Introductionmentioning

confidence: 99%

“…The interface properties of SiO 2 and Al 2 O 3 /InGaAs MOS interfaces with the InGaAs nitrided layers are addressed [48,49]. Among a variety of gate insulators and/or interface control layers on Ge, attention has recently been paid more to GeO 2 /Ge interfaces, because of the superior interface properties [7,8,[15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30]. We have already shown that GeO 2 /Ge interfaces with a quite low interface state density can be realized by direct thermal oxidation of Ge substrates [21,23].…”

Section: Introductionmentioning

confidence: 99%

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(Invited) MOS Interface Control Technologies for III-V/Ge Channel MOSFETs

et al. 2011

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MOSFETs using channel materials with low effective mass have been regarded as strongly important for obtaining high current drive and low supply voltage CMOS under sub 10 nm regime. From this viewpoint, attentions have recently been paid to III-V and Ge channels. However, one of the most critical issues for realizing Ge/III-V MOSFETs is gate insulator formation with superior MOS interface quality on Ge/III-V. In this paper, we focus on the possible solutions for gate stack technologies on Ge/III-V. As for Ge, GeO 2 /Ge interfaces have been regarded as promising. However, these interfaces have still employed thick GeO 2 layers. Recently, we have succeeded in thin EOT gate stacks with Ge oxide interfacial layers by using ECR plasma post oxidation. The high quality Al 2 O 3 /GeO x /Ge gate stacks were fabricated by exposing the ALD Al 2 O 3 /Ge structures to ECR oxygen plasma and oxidizing the Ge surface through the very thin ALD Al 2 O 3 layer. We present our recent results of the interface properties using this interface. As for InGaAs channels, we have also proposed a novel interfacial control technology utilizing InGaAs surface nitridation by ECR nitrogen plasma and successive post metallization annealing. This interfacial layer combined with an ECR sputtering SiO 2 or an ALD Al 2 O 3 gate insulator is shown to reduce D it down to low order of 10 11 cm -2 eV -1 . The physical origin of this D it reduction and the role of the nitridation are discussed.

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Interface-Engineered Ge (100) and (111), N- and P-FETs with High Mobility

Cited by 65 publications

References 6 publications

1 [micro sign]m gate length, In0.75Ga0.25As channel, thin body n-MOSFET on InP substrate with transconductance of 737 [micro sign]S/μm

1 [micro sign]m gate length, In0.75Ga0.25As channel, thin body n-MOSFET on InP substrate with transconductance of 737 [micro sign]S/μm

Interface-Controlled Self-Align Source/Drain Ge p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors Fabricated Using Thermally Oxidized GeO₂Interfacial Layers

(Invited) MOS Interface Control Technologies for III-V/Ge Channel MOSFETs

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Interface-Engineered Ge (100) and (111), N- and P-FETs with High Mobility

Cited by 65 publications

References 6 publications

1 [micro sign]m gate length, In0.75Ga0.25As channel, thin body n-MOSFET on InP substrate with transconductance of 737 [micro sign]S/μm

1 [micro sign]m gate length, In0.75Ga0.25As channel, thin body n-MOSFET on InP substrate with transconductance of 737 [micro sign]S/μm

Interface-Controlled Self-Align Source/Drain Ge p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors Fabricated Using Thermally Oxidized GeO2Interfacial Layers

(Invited) MOS Interface Control Technologies for III-V/Ge Channel MOSFETs

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Interface-Controlled Self-Align Source/Drain Ge p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors Fabricated Using Thermally Oxidized GeO₂Interfacial Layers