Interface-Controlled Self-Align Source/Drain Ge p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors Fabricated Using Thermally Oxidized GeO₂Interfacial Layers

Abstract

We have successfully fabricated high hole mobility Ge p-channel metal-oxide-semiconductor field-effect transistors (p-MOSFETs) with GeO 2 /Ge formed by direct thermal oxidation, which can yield a significantly low interface trap density (D it ). Al 2 O 3 films are employed as capping layers for protecting the GeO 2 /Ge MOS interfaces during the MOSFET fabrication processes. The source/drain (S/D) regions are formed by boron ion implantation in a self-align way with Al gate metal. The good MOS interface properties are found to be maintained even after the activation annealing at temperatures sufficient for obtaining the excellent junction properties. The fabricated MOSFETs exhibit high source and drain on/off current ratios of 10 5 -10 4 and a high peak hole mobility of 575 cm 2 V À1 s À1 at maximum, both of which are attributable to the excellent GeO 2 /Ge MOS interface properties. The effects of the substrate impurity concentration and the thickness of GeO 2 on the hole mobility are examined. It is found from the results for different substrate impurity concentrations that the universal curve between hole mobility and the effective field E eff holds for ¼ 1=3. We also investigate the impact of the oxidation temperature dependence on hole mobility in order to examine the scattering mechanism limiting the mobility of GeO 2 /Ge interfaces through the modulation of the MOS interfaces by changing oxidation temperature. It is found that the mobility in low-temperature and low-surface carrier density (N s ) regions is well corrected with D it evaluated from S factors in MOSFETs. In addition, it is revealed from transmission electron microscopy analyses that the interface roughness between GeO 2 and Ge is reduced with increasing oxidation temperature. From these experimental results, the higher mobility of GeO 2 /Ge p-MOSFET at higher oxidation temperatures can be explained by the reduction in the density of Coulomb scattering centers and surface roughness at elevated Ge oxidation temperatures. #

Hole Mobility Boost of Ge p-MOSFETs by Composite Uniaxial Stress and Biaxial Strain

“…Calculated hole mobility on (001) substrate along [110] direction in Si, Ge, Ge/GeO 2 and strained Ge/relaxed Si 0.6 Ge 0.4 channel with the comparison of our experimental work (triangle) and previous data[3][4][5] .…”

Challenges and opportunities in advanced Ge pMOSFETs

“…Good quality GeO 2 passivation has been achieved by several oxidation methods, including in situ thermal oxidation [122,141], ozone oxidation [142], high-pressure oxidation [123,124,140] and radical oxidation [143]. It is crucial to prevent direct contact of GeO 2 with water or air moisture by capping the interfacial layer by a high-k dielectric like Al 2 O 3 [28,143] or a rare earth oxide cap, e.g.…”

(Invited) Gate Stack and Source/Drain Junction Formations for High-Mobility Ge MOSFETs

“…μ e and μ h versus N s characteristics of Ge n-and p-MOSFETs. For comparison, the μ e and μ h of Si MOSFETs are also shown (4,18).…”