Interface-Controlled Self-Align Source/Drain Ge p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors Fabricated Using Thermally Oxidized GeO<sub>2</sub>Interfacial Layers

Nakakita, Yosuke; Nakakne, Ryosho; Sasada, Takashi; Takenaka, Mitsuru; Takagi, Shinichi

doi:10.7567/jjap.50.010109

Cited by 21 publications

(7 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Among a variety of gate insulators and/or interface control layers on Ge, attention has recently been paid more to GeO 2 /Ge interfaces, because of the superior interface properties [7,8,[15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30]. We have already shown that GeO 2 /Ge interfaces with a quite low interface state density can be realized by direct thermal oxidation of Ge substrates [21,23].…”

Section: Ge Gate Stack Technologiesmentioning

confidence: 99%

“…As for Ge MOS/MIS structures, the gate stacks composed of high k layers and interfacial control layers have been mainly studied [7,8], because the difficulty in realizing superior MOS properties in direct interfaces between Ge and high k materials [9]. A variety of interfacial layers such as SiO 2 /Si [10][11][12][13][14], GeO 2 [7,8,[15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30], GeON [19,[31][32][33] and Ge 3 N 4 [16,[34][35][36][37] and their MOS interface properties have already been reported. Among them, GeO 2 /Ge interfaces have recently been regarded as one of the most superior Ge MOS interfaces [7,8,[15][16][17][18][19][20][21][22][23][24]…”

Section: Introductionmentioning

confidence: 99%

“…A variety of interfacial layers such as SiO 2 /Si [10][11][12][13][14], GeO 2 [7,8,[15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30], GeON [19,[31][32][33] and Ge 3 N 4 [16,[34][35][36][37] and their MOS interface properties have already been reported. Among them, GeO 2 /Ge interfaces have recently been regarded as one of the most superior Ge MOS interfaces [7,8,[15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30]. Actually...…”

Section: Introductionmentioning

confidence: 99%

“…Among them, GeO 2 /Ge interfaces have recently been regarded as one of the most superior Ge MOS interfaces [7,8,[15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30]. Actually, high performance n-and p-MOSFETs with this GeO 2 /Ge interface control layer have already been demonstrated by many research groups [8,18,19,22,[24][25][26][27][28][29][30]. However, co-existence of thin equivalent oxide thickness (EOT), low interface state density (D it ) and high channel mobility is still challenging for gate stacks using this GeO 2 /Ge interface control layer.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

(Invited) MOS Interface Control of High Mobility Channel Materials for Realizing Ultrathin EOT Gate Stacks

et al. 2013

View full text Add to dashboard Cite

One of the most critical issues for Ge/III-V MOSFETs, which have been regarded as a promising CMOS structure under sub 10 nm regime, is gate insulator formation satisfying the requirements of MOS interface quality and thin equivalent oxide thickness (EOT). In this paper, we focus on viable gate stack technologies realizing these requirements. As for Ge gate stacks, we present a ultrathin EOT Al 2 O 3 /GeO x /Ge gate stack fabricated by a plasma post oxidation method and pMOSFETs using this gate stack. The GeO x /Ge MOS interface properties are systemically examined, and the relations of the interface state density (D it ) with the GeO x thickness and the chemical conditions are studied. (100) Ge pMOSFETs using this gate stack is demonstrated with EOT down to 0.98 nm and high hole peak mobility of 401 cm 2 /Vs. As for InGaAs gate stacks, we show the impact of Al 2 O 3 inter-layers on interface properties of HfO 2 /InGaAs MOS interfaces. It is found that the insertion of 0.2-nm-thick ultrathin Al 2 O 3 inter-layer can effectively improve the HfO 2 /InGaAs interface properties such as the frequency dispersion and the stretch-out of C-V characteristics and D it . The 1-nm-thick capacitance equivalent thickness (CET) in the HfO 2 /Al 2 O 3 /InGaAs MOS capacitors is realized with good interface properties and low gate leakage of 2.4×10 -2 A/cm 2 .

show abstract

Section: Ge Gate Stack Technologiesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

(Invited) MOS Interface Control of High Mobility Channel Materials for Realizing Ultrathin EOT Gate Stacks

et al. 2013

View full text Add to dashboard Cite

show abstract

“…The IPL helps to passivate the surface by reducing the defect concentration, thereby forming a higher quality interface with Ge. By careful selection and control of the oxidation temperature and oxidation time, Nakakita et al 53 were able to demonstrate metal-oxidesemiconductor capacitors (MOS-Cs) and MOSFET gate stacks consisting of Al 2 O 3 /GeO x /Ge with low D it values of ∼2 × 10 11 −4 × 10 11 eV −1 cm −2 , where the GeO x was thermally formed at 450−550 °C oxidation temperature for different thickness. This lower D it value is correlated with a higher peak hole mobility of 575 cm 2 V −1 s −1 and I ON /I OFF of ∼10 5 of a Ge MOSFET.…”

Section: Introductionmentioning

confidence: 99%

High-κ Gate Dielectric on Tunable Tensile Strained Germanium Heterogeneously Integrated on Silicon: Role of Strain, Process, and Interface States

Hudait,

Clavel,

Karthikeyan

et al. 2023

ACS Appl. Electron. Mater.

View full text Add to dashboard Cite

Tensile strained germanium (ε-Ge) layers heterogeneously integrated on Si substrates are of technological importance for nanoscale transistors and photonics. In this work, the tunable tensile strained (0% to 1.2%) ε-Ge layers were grown by solid source molecular beam epitaxy using GaAs and linearly graded In x Ga1–x As as intermediate buffers, and their structural and metal-oxide semiconductor capacitor (MOS-Cs) properties were analyzed as a function of strain and process conditions. X-ray topography measurements displayed no visible thermal crack and a low thermal stress of ∼50 MPa. Temperature dependent strain relaxation properties, studied by X-ray and Raman analyses, confirmed that the tensile strain amount of 1.2% was well preserved within the ε-Ge layer when annealed up to 550 °C. Further, transmission electron microscopic study revealed a good quality 1.2% strained ε-Ge/In0.17Ga0.83As heterointerface. In addition, unstrained Ge (0% ε-Ge) MOS-Cs with atomic layer deposited Al2O3 and thermally grown GeO2 composite gate dielectrics of varying oxidation times (0.25–7.5 min) at 550 °C exhibited a low interface state density (D it) of ∼2.5 × 1011 eV–1 cm–2 at 5 min oxidation duration. The minimum oxidation time needed for good capacitance–voltage (C–V) characteristics on 0.2% ε-Ge is inadequate to accomplish similar C–V characteristics on 1.2% ε-Ge MOS-C, due to the higher strain field impeding the formation of the GeO2 interface passivation layer at lower oxidation duration. In addition, with the trade-off between the minimum D it and minimum equivalent oxide thickness values, ∼1.5 min is found to be an optimum oxidation time for good quality 1.2% ε-Ge MOS-C. The minimum D it values of 1.36 × 1011 and 2.06 × 1011 eV–1 cm–2 for 0.2% and 1.2% ε-Ge, respectively, were determined for 4 nm Al2O3 with 5 min thermal oxidation at 550 °C. Therefore, the successful monolithic integration of tunable tensile strain Ge on Si with structural defects and MOS-Cs analyses offer a path for the development of tensile strained Ge-based nanoscale transistors.

show abstract

First-Principles Modelling of Vibrational Modes in Defective Oxides and Correlation with IETS

Scalise

2014

Vibrational Properties of Defective Oxides and 2D Nanolattices

View full text Add to dashboard Cite

Interface-Controlled Self-Align Source/Drain Ge p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors Fabricated Using Thermally Oxidized GeO₂Interfacial Layers

Cited by 21 publications

References 18 publications

(Invited) MOS Interface Control of High Mobility Channel Materials for Realizing Ultrathin EOT Gate Stacks

(Invited) MOS Interface Control of High Mobility Channel Materials for Realizing Ultrathin EOT Gate Stacks

High-κ Gate Dielectric on Tunable Tensile Strained Germanium Heterogeneously Integrated on Silicon: Role of Strain, Process, and Interface States

First-Principles Modelling of Vibrational Modes in Defective Oxides and Correlation with IETS

Contact Info

Product

Resources

About

Interface-Controlled Self-Align Source/Drain Ge p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors Fabricated Using Thermally Oxidized GeO2Interfacial Layers

Cited by 21 publications

References 18 publications

(Invited) MOS Interface Control of High Mobility Channel Materials for Realizing Ultrathin EOT Gate Stacks

(Invited) MOS Interface Control of High Mobility Channel Materials for Realizing Ultrathin EOT Gate Stacks

High-κ Gate Dielectric on Tunable Tensile Strained Germanium Heterogeneously Integrated on Silicon: Role of Strain, Process, and Interface States

First-Principles Modelling of Vibrational Modes in Defective Oxides and Correlation with IETS

Contact Info

Product

Resources

About

Interface-Controlled Self-Align Source/Drain Ge p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors Fabricated Using Thermally Oxidized GeO₂Interfacial Layers