“…The in-plane lattice mismatch can be minimized by engineering the interfaces (between InAs and GaSb layers) which is known to have a profound effect on the device performance [10,[13][14][15][16]. Introducing special interface recipes during the growth of SLs to intentionally form 0 to 1 monolayer (ML) thick GaAs-and/or InSb-like interfaces are widely used by many research groups [8,13,14,[16][17][18][19][20][21][22]. Because of the differences in the lattice parameters, the structure can be either under compressive or tensile strain depending on the interfaces.…”