Interest of SiCO low k=4.5 spacer deposited at low temperature (400°C) in the perspective of 3D VLSI integration

Benoît, Daniel; Mazurier, J.; Varadarajan, B.; Chhun, S.; Lagrasta, S.; Gaumer, C.; Galpin, D.; Fenouillet-Béranger, C.; Vo-Thanh, D.; Barge, D.; Duru, Romain; Beneyton, R.; Gong, B.; Sun, Noel; Chauvet, Nicolas; Ruault, P.; Winandy, D.; Schravendijk, B. van; Meijer, Peter; Hinsinger, O.

doi:10.1109/iedm.2015.7409656

Cited by 8 publications

(5 citation statements)

References 5 publications

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“…Thus, innovative process integration schemes are demanded to minimise FinFET parasitic capacitance. It has generated great interest to explore alternative gate sidewall spacer materials with dielectric constant (k value) lower than traditional silicon nitride (SiN, k = 7.0) to reduce the capacitance between the gate and the source/drain electrodes [5,6]. However, integration of any novel low-dielectric constant (low-k) spacer material at advanced nodes is an extremely challenging task as the spacer material must be compatible with complex manufacturing processes to meet technology ground rules [7,8].…”

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confidence: 99%

Hybrid low‐ k spacer scheme for advanced FinFET technology parasitic capacitance reduction

Wang

et al. 2020

Electron. lett.

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Low-dielectric constant (low-k) material is critical for advanced FinFET technology parasitic capacitance reduction to enable lowpower and high-performance applications. Silicon Oxycarbonnitride (SiOCN) is one of the most promising low-k materials for FinFET gate sidewall spacer. The k value of SiOCN can be controlled in the range of 4.1-5.2 by modifying the chemical contents during the deposition process. However, the integration of SiOCN with k value lower than 5.2 for advanced FinFET technology faces substantial challenges associated with the material damage from subsequent manufacturing processes. Here, the authors demonstrate a hybrid low-k spacer scheme on a fully integrated 7 nm FinFET technology platform, in which SiOCN with k value of 4.5 was successfully integrated along the sidewalls of the gate electrode as spacer while retaining the structural integrity and dielectric properties. Device characterisation on the hybrid low-k spacer scheme (k = 4.5) demonstrated 12/11% reduction in P/NFET overlap capacitance (C OV) and 3% reduction in ring oscillator effective capacitance (C EFF) in comparison to the baseline reference using SiOCN with k value of 5.2 as spacer. Furthermore, reliability characterisation confirmed the dielectric breakdown voltage (V BD) and leakage current (I LKG) of the hybrid low-k spacer (k = 4.5) were comparable to the baseline reference (k = 5.2), meeting the technology requirements.

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confidence: 99%

Hybrid low‐ k spacer scheme for advanced FinFET technology parasitic capacitance reduction

Wang

et al. 2020

Electron. lett.

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“…Moreover, it is combined with repeated etching cycles. The accuracy order of the magnitude reached 0.3-0.4 nm [17] . Hence, it is a promising candidate process to be applied in selfaligned contacts and spacer etching.…”

Section: Alementioning

confidence: 95%

Advanced process and electron device technology

Zhang¹,

Su²,

Chang³

et al. 2022

Tsinghua Sci. Technol.

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This article reviews advanced process and electron device technology of integrated circuits, including recent featuring progress and potential solutions for future development. In 5 years, for pushing the performance of fin field-effect transistors (FinFET) to its limitations, several processes and device boosters are provided. Then, the three-dimensional (3D) integration schemes with alternative materials and device architectures will pave paths for future technology evolution. Finally, it could be concluded that Moore's law will undoubtedly continue in the next 15 years.

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“…Bent et al successfully fabricated silicon oxycarbide (SiOC) films using precursorcontaining carbon chains within the molecule and oxidants such as O 3 and H 2 O through MLD, reporting a low dielectric constant of 3.6-3.7 [18][19][20]. Additionally, SiOC films deposited via MLD exhibited excellent thermal stability even at temperatures above 400 • C [18,21]. They showed minimal thickness loss at temperatures exceeding 600 • C, demonstrating the higher thermal stability of MLD-deposited films than that of the films prepared through other methods.…”

Section: Introductionmentioning

confidence: 99%

Synthesis of low-k SiONC thin films by plasma-assisted molecular layer deposition with tetraisocyanatesilane and phloroglucinol

Park,

Yang,

Kim

et al. 2024

Nanotechnology

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Low-k SiONC thin films with excellent thermal stabilities were deposited using plasma-assisted molecular layer deposition (PA-MLD) with a tetraisocyanatesilane (Si(NCO)4) precursor, N2 plasma, and phloroglucinol (C6H3(OH)3). By adjusting the order of the N2 plasma exposure steps within the PA-MLD process, we successfully developed a deposition technique that allows accurate control of thickness at the Ångström level via self-limiting reactions. The thicknesses of the thin films were measured through spectroscopic ellipsometry (SE). By tuning the N2 plasma power, we facilitated the formation of -NH2 sites for phloroglucinol adsorption, achieving a growth per cycle of 0.18 Å/cycle with 300 W of N2 plasma power. Consequently, the thickness of the films increased linearly with each additional cycle. Moreover, the organic linkers within the film formed stable bonds through surface reactions, resulting in a negligible decrease in thickness of approximately −11% even upon exposure to a high annealing temperature of 600 ℃. This observation was confirmed by SE, distinguishing the as-prepared film from previously reported low-k films that fail to maintain their thickness under similar conditions. X-ray photoelectron spectroscopy (XPS) and current–voltage (I–V) and capacitance–voltage (C–V) measurement were conducted to evaluate the composition, insulating properties, and dielectric constant according to the deposition and annealing conditions. XPS results revealed that as the plasma power increased from 200 to 300 W, the C/Si ratio increased from 0.37 to 0.67, decreasing the dielectric constant from 3.46 to 3.12. Furthermore, there was no significant difference in the composition before and after annealing, and the hysteresis decreased from 0.58 to 0.19 V owing to defect healing, while maintaining the leakage current density, breakdown field, and dielectric constant. The low dielectric constant, accurate thickness control, and excellent thermal stability of this MLD SiONC thin film enable its application as an interlayer dielectric in back-end-of-line process.

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Interest of SiCO low k=4.5 spacer deposited at low temperature (400°C) in the perspective of 3D VLSI integration

Cited by 8 publications

References 5 publications

Hybrid low‐ k spacer scheme for advanced FinFET technology parasitic capacitance reduction

Hybrid low‐ k spacer scheme for advanced FinFET technology parasitic capacitance reduction

Advanced process and electron device technology

Synthesis of low-k SiONC thin films by plasma-assisted molecular layer deposition with tetraisocyanatesilane and phloroglucinol

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