Intercomparison of Methods for Detecting and Characterizing Voids in Bonded Wafer Pairs

Abstract

The Wafer Bond Task Force of the SEMI MEMS Standards Committee has begun a round robin experiment to evaluate methods for identifying and characterizing voids in bonded wafer pairs for three-dimensional integrated circuit (3D IC) applications. Due to the numerous process steps that the wafers have undergone and the presence of Through-Silicon Vias (TSVs), bonded wafers containing 3D ICs are expected to suffer a higher rate of postbonding voids than other bonding applications. In addition, 3D ICs will likely be more sensitive to small voids than other bond applications. In this round robin experiment eight approaches to void metrology are being compared by 13 participating laboratories to highlight the relative abilities of each of these metrologies to identify potentially killer defects.

(Invited) Metrology for 3D Integration

“…SEMI draft document 5270 is being developed to provide a guide to the metrology tools that identify and characterize voids between bonded wafers. A number of tools have been identified that are capable of detecting and/or characterizing bond voids, and a round robin experiment is currently underway to provide a guide to the capabilities and limitations of each of these tools (5).…”

A near-infrared confocal scanner

“…Since silicon and other semiconductor materials, while opaque to visible light, are relatively transparent to NIR wavelengths longer than 1100 nm [7][8][9], it is possible to inspect within and beneath semiconductor materials in a non-destructive way without cross-sectioning or otherwise disrupting the samples. NIR microscopy is widely used in the semiconductor industry, especially in 3D packaging technologies, for inspecting subsurface defects and structures of semiconductor and microelectro-mechanical system (MEMS) devices [1,6,7,10]. Also, the NIR imaging technique can be used during the manufacturing process, such as during overlay alignment, to improve the TSV quality and to achieve the required 3D stack yields.…”