Metrology Needs for 2.5D/3D Interconnects

Vartanian, Victor; Allen, Richard A.; Smith, Larry; Hummler, Klaus; Olson, Steve; Sapp, Brian

doi:10.1002/9783527670109.ch29

Cited by 2 publications

(1 citation statement)

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“…In addition to providing device performance and density gains, three-dimensional stacked integrated circuits (3DS-ICs) will enable heterogeneous integration, combining functions that cannot otherwise be integrated in a single device due to process incompatibilities. This paper examines the metrologies needed to implement 3DS-ICs (1), focusing on the metrologies included in current SEMI documents, both published Standards and on-going Standards development. Of the fourteen SEMI documents completed or under development by the 3DS-IC Committee, ten have metrology as their primary focus while the recommendations of an eleventh was based on the results of a multi-participant experiment.…”

Section: Introductionmentioning

confidence: 99%

(Invited) Metrology for 3D Integration

Allen¹,

Vartanian²,

Read³

et al. 2014

ECS Trans.

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Three-dimensional stacked integrated circuit (3DS-IC) fabrication requires complex technologies such as high-aspect ratio throughsilicon vias (TSVs), wafer thinning, thin wafer handling and processing, and bonding of thin wafers with complex patterned surfaces. Each of these new fabrication steps is associated with metrology challenges.The SEMI 3DS-IC Committee is developing a set of guides to assist the 3DS-IC community in addressing these challenges by identifying metrology solutions. In this paper we provide an overview of the metrology needs for 3DS-IC, identify metrology solutions, and provide examples from SEMI standards describing methods for characterizing the quality and strength of bonds between wafers.

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Section: Introductionmentioning

confidence: 99%