InterChip via technology for vertical system integration

Ramm, Peter; Bonfert, Detlef; Gieser, H.; Haufe, J.; Iberl, F.; Klumpp, Armin; Kux, A.; Wieland, Robert

doi:10.1109/iitc.2001.930046

Cited by 61 publications

(21 citation statements)

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“…Various kinds of 3D devices or 3D LSIs have been proposed so far [3,4,5,6,7,8,9,10,11,12,13,14,15,16]. The first 3D LSI test chip having three device layers was fabricated using the poly-Si film which is re-crystallized by laser annealing [3].…”

Section: Present Situation Of 3d Integration Technologymentioning

confidence: 99%

Recent progress in 3D integration technology

Koyanagi

2015

IEICE Electron. Express

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3D integration technology is the key for future LSIs with highperformance, low-power and multi-functionality. Especially, to mitigate various concerns caused by device scaling down to 10 nm or less, it is indispensable to introduce a new concept of heterogeneous 3D integration in which various kinds of materials, devices and technologies are integrated on a Si substrate. Future prospects of such a heterogeneous 3D integration technology has been discussed representing typical examples of heterogeneous 3D LSIs after the present situation of 3D integration technology is described.

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Section: Present Situation Of 3d Integration Technologymentioning

confidence: 99%

Recent progress in 3D integration technology

Koyanagi

2015

IEICE Electron. Express

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“…The so-called Inter-Chip-Via (ICV) technology is described in detail in the literature [19][20][21][22]. substrate (through silicon via), providing a vertical interconnect between metallization levels of both devices.…”

Section: Vertical System Integration Using Adhesive Bonding -The Icv mentioning

confidence: 99%

“…For void-less filling of high aspect ratio vias, highly conformal MOCVD processes are of advantage. Excellent results were achieved using both CVD tungsten and CVD copper (in both cases with CVD-TiN as seed layer) [24]. Subsequently, for so-called metal plug formation a suitable metal etch back process is applied.…”

Section: Vertical System Integration Using Adhesive Bonding -The Icv mentioning

confidence: 99%

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Wafer‐Level 3D System Integration

Ramm

Wolf

Wunderle

2008

Handbook of 3D Integration

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“…But it needs special chip design and the relatively complicated process steps restricts this method to semiconductor industry. More details to this procedure are described by Ramm et al (2001).…”

mentioning

confidence: 99%

Ultra thin ICs and MEMS elements: techniques for wafer thinning, stress-free separation, assembly and interconnection

Feil

Alder

Klink

et al. 2003

Microsystem Technologies

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Ultra thin chips with a thickness below 30 lm offer low system height, low topography and show enhanced mechanical flexibility. These properties enable diverse use possibilities and new applications. However, advanced wafer thinning, adapted assembly and interconnection methods are required for this technology. A new process scheme is proposed that allows manufacturing of ultra thin fully processed wafers. Secure handling is achieved by means of carrier substrates using reversible adhesive tapes for connection of support and device wafers. Well established backgrinding and etching techniques are used for wafer thinning. To avoid mechanical damage of thin ICs the ''Dicing-by-Thinning'' (DbyT) concept is introduced to process flow. Best results are obtained when preparing dry etched chip grooves at front side of device wafer and opening these trenches during backside thinning. The new process scheme was also applied to wafers with highly topographic surfaces. Results of 40 lm thin wafers with 15 lm high Nickel bumps are presented. Three different assembly methods are described, interconnection through the thin chip, face down assembly and isoplanar contacting.

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InterChip via technology for vertical system integration

Cited by 61 publications

References 1 publication

Recent progress in 3D integration technology

Recent progress in 3D integration technology

Wafer‐Level 3D System Integration

Ultra thin ICs and MEMS elements: techniques for wafer thinning, stress-free separation, assembly and interconnection

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