Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461) 2001
DOI: 10.1109/iitc.2001.930046
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InterChip via technology for vertical system integration

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Cited by 61 publications
(21 citation statements)
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“…Various kinds of 3D devices or 3D LSIs have been proposed so far [3,4,5,6,7,8,9,10,11,12,13,14,15,16]. The first 3D LSI test chip having three device layers was fabricated using the poly-Si film which is re-crystallized by laser annealing [3].…”
Section: Present Situation Of 3d Integration Technologymentioning
confidence: 99%
“…Various kinds of 3D devices or 3D LSIs have been proposed so far [3,4,5,6,7,8,9,10,11,12,13,14,15,16]. The first 3D LSI test chip having three device layers was fabricated using the poly-Si film which is re-crystallized by laser annealing [3].…”
Section: Present Situation Of 3d Integration Technologymentioning
confidence: 99%
“…The so-called Inter-Chip-Via (ICV) technology is described in detail in the literature [19][20][21][22]. substrate (through silicon via), providing a vertical interconnect between metallization levels of both devices.…”
Section: Vertical System Integration Using Adhesive Bonding -The Icv mentioning
confidence: 99%
“…For void-less filling of high aspect ratio vias, highly conformal MOCVD processes are of advantage. Excellent results were achieved using both CVD tungsten and CVD copper (in both cases with CVD-TiN as seed layer) [24]. Subsequently, for so-called metal plug formation a suitable metal etch back process is applied.…”
Section: Vertical System Integration Using Adhesive Bonding -The Icv mentioning
confidence: 99%
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“…But it needs special chip design and the relatively complicated process steps restricts this method to semiconductor industry. More details to this procedure are described by Ramm et al (2001).…”
mentioning
confidence: 99%