Inter-Strata Connection Characteristics and Signal Transmission in Three-Dimensional (3D) Integration Technology

Alam, Syed Q.; Jones, Robert E.; Rauf, Shahid; Chatterjee, Ritwik

doi:10.1109/isqed.2007.92

Cited by 45 publications

(19 citation statements)

References 3 publications

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“…A few researchers have reported measured via inductances that range from as low as 4 pH to as high as 255 pH [9], [13], [16]. Alternatively, preliminary work on modeling 3-D vias has primarily focused on the resistance and capacitance of simple structures to verify measured RLC impedances while providing some physical insight into the 3-D via to 3-D via capacitive coupling [8], [13]- [15]. Furthermore, preliminary work in the electrical modeling of bundled TSVs has been reported in [17]- [19].…”

Section: Introductionmentioning

confidence: 99%

Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance

Savidis

Friedman

2009

IEEE Trans. Electron Devices

180

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Abstract-Closed-form expressions of the resistance, capacitance, and inductance for interplane 3-D vias are presented in this paper. The closed-form expressions account for the 3-D via length, diameter, dielectric thickness, and spacing to ground. A 3-D numerical simulation is used to extract electromagnetic solutions of the resistance, capacitance, and inductance for comparison with the closed-form expressions, revealing good agreement between simulation and the physical models. The maximum error for the resistance, capacitance, and inductance is less than 8%.

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Section: Introductionmentioning

confidence: 99%

Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance

Savidis

Friedman

2009

IEEE Trans. Electron Devices

180

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“…A few researchers have reported measured via inductances that range from as low as 42 pH to as high as 255 pH [3], [9]. Alternatively, 3-D via modeling has primarily been applied to simple structures to verify the measured RLC values while providing some insight into 3-D via to 3-D via capacitive coupling [2], [7]. This paper expands on this early work, and adds new insight towards shielding both capacitive and inductive coupling.…”

Section: Introductionmentioning

confidence: 93%

“…Due to the large variation in the 3-D via diameter, length, dielectric thickness, and fill material, a wide range of measured resistances, capacitances, and inductances have been reported in the literature. Single 3-D via resistance values vary from 20 mΩ to as high as 350 Ω [2]- [6], while reported capacitances vary from 40 fF to over 1 pF [7], [8]. A few researchers have reported measured via inductances that range from as low as 42 pH to as high as 255 pH [3], [9].…”

Section: Introductionmentioning

confidence: 99%

Electrical modeling and characterization of 3-D vias

Savidis

Friedman

2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-Electrical characterization of the resistance, capacitance, and inductance of inter-plane 3-D vias is presented in this paper. Both capacitive and inductive coupling between multiple 3-D vias is described as a function of the separation distance and plane location. The effects of placing a third shield via between two signal vias is investigated as a means to limit the capacitive coupling. The location of the return path is examined to determine the best placement of a 3-D via to reduce the overall loop inductance. Based on the extracted resistance, capacitance, and inductance, the L/R time constant is shown to be much larger than the RC time constant, demonstrating that the 3-D via structure investigated in this paper is inductively limited rather than capacitively limited.

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“…They provide RC analytical models [16], high frequency RLCG models [17][18][19] and compact models [20]. In this way, in 2005 a TSV model built from RF measurements was proposed by Leung et al for 400 [17].…”

Section: Overview Of Tsv Modeling Techniquesmentioning

confidence: 99%

Integration and Frequency Dependent Parametric Modeling of Through Silicon via Involved in High Density 3D Chip Stacking

Cadix

Fuchs²,

Rousseau³

et al. 2010

ECS Trans.

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Evaluation of Through Silicon Via (TSV) electrical performance is hardly required today to improve heterogeneous 3D chip performance in the frame of a "more than Moore" approach. Accurate modeling of TSV is consequently essential to perform design optimizations and process tuning. This paper proposes a methodology based on RF characterizations and simulations, leading to a frequency dependent analytical model including MOS effect of high aspect ratio TSV. Specific test structures integrated on both floating Si bulk and CMOS 65 nm active wafers according to a face-to-face Via Last After Bonding process enable C(V) and RF measurements. TSV equivalent model including all substrate effects is proposed according to CMOS 65 nm specificities (voltage, frequency, dimensions and Si conductivity) and implemented in SPICE simulator to predict TSV impact on signal propagation.

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Inter-Strata Connection Characteristics and Signal Transmission in Three-Dimensional (3D) Integration Technology

Cited by 45 publications

References 3 publications

Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance

Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance

Electrical modeling and characterization of 3-D vias

Integration and Frequency Dependent Parametric Modeling of Through Silicon via Involved in High Density 3D Chip Stacking

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