Intelligent Signal Gating-Aware Energy-Efficient 8-Bit FinFET Arithmetic and Logic Unit

Ajitha, D.; Reddy, M. Chandra Sekhar

doi:10.1007/s00034-021-01775-w

Cited by 2 publications

(2 citation statements)

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“…From the simulations, it is observed that the proposed DCHS resulted in superior performance, because it performs subtraction using twos complement addition process. Table 9 compares the performance of the proposed DCHAS with various state of art combined adders and subtractors like GAEAS [19], FHAS [20], CNTFET-AS [21], and MRAS [23]. From the simulations, it is observed that the proposed DCHAS resulted in superior performance, because it performs subtraction using twos complement addition process.…”

Section: Resultsmentioning

confidence: 99%

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Design and Implementation of ALU Using Graphene Nanoribbon Field‐Effect Transistor and Fin Field‐Effect Transistor

Florance

Prabhakar

Mishra

2022

Journal of Nanomaterials

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Arithmetic and logical unit (ALU) are the core operational programmable logic block in microprocessors, microcontrollers, and real-time-integrated circuits. The conventional ALUs were developed using complementary metal oxide semiconductor (CMOS) technology, which resulted in excessive power consumptions, path delays, and number of transistors. Therefore, this article focuses on the design and development of hybrid delay-controlled reconfigurable ALU (DCR-ALU) using field-effect transistor (FinFET) and graphene nanoribbon field-effect transistor (GnrFET) technologies. Initially, a novel carry output predictable full adder (COPFA) and carry input selectable full adders (CISFA) are developed using multiplexer selection logic; then, delay-controlled hybrid adder (DCHA) and delay-controlled hybrid subtractor (DCHS) are developed using these full adders. In addition, a unified delay-controlled hybrid adder and subtractor (DCHAS) is developed by combining these DCHA and DCHS. Further, a delay controller array multiplier (DCAM) also developed using DCHA modules. Finally, DCR-ALU is developed by adopting the DCHAS, DCAM, and logical operations. The obtained simulation results shows that the proposed nanotechnology-based models outperformed the conventional adders and subtractors in terms of area, power, and delay reduction.

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Section: Resultsmentioning

confidence: 99%

“…In [19], the authors developed the gating-aware energy adders and subtractors (GAEAS) for power utilization that has transformation. For the reduction of circuit consumption, BEC is utilized in the modified quantum adders instead of CSLA and RCA with increasing the delay slightly.…”

Section: Related Workmentioning

confidence: 99%